Transformation-Based Logic Design for RSFQ Logic Circuits

Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi

A method for converting a CMOS logic circuit design to an efficient RSFQ design, which minimizes the number of flip-flops during conversion, is proposed. In an RSFQ circuit, each data input terminal of a logic gate has latching function, and the function is enabled or disabled depending on the order of the arrivals of the data pulse and the corresponding clock pulse. The number of flip-flops is minimized by the use of the latching functions through arrangement of the order of pulse arrivals of each gate and also by circuit retiming. A conversion tool based on the proposed method has been developed. Conversion results of CMOS benchmark circuits show that most of the flip-flops in the circuits are eliminated by the proposed method. A 4-bit RSFQ processor was successfully designed by an existing CMOS design tool and the developed conversion tool.

Lieze Schindler, Coenrad Johann Fourie

In contrast to transistor-based semiconductor circuits, there is currently no widely accepted formalized circuit theory or design methodology for superconductor rapid single flux quantum (RSFQ) logic circuits. Experienced designers intuitively consider flux loops, nodal phase, and branch currents when making design choices, but the lack of a formalized design process makes it difficult for inexperienced RSFQ circuit designers to construct a functioning logic cell without a reference. This results in new circuit designers, mostly recycling templates from published circuit designs without fully understanding why the circuits function as they do. Inexperienced RSFQ circuit designers often follow an iterative process where cell parameter values are adjusted, and the cell is run through electronic simulation engines until the desired functionality is reached. We propose the development of a formalized circuit design theory for RSFQ logic from first principles using phase-based circuit analysis. The circuit is designed using dc analysis to establish the dc operating point of the circuit. Phase-based analysis and simulation are then used to verify the dynamic circuit functionality. To demonstrate this method, we discuss examples for well-known RSFQ cells. We analyze the initial operating margins of these designs and discuss design accuracy and efficiency. Methods for current regulation to minimize current leakage between cells are discussed. We also present how this design methodology can be used to design new circuits such as an RSFQ XNOR cell. We investigate how an inverting (NOT) cell can be combined with other logic cells to minimize cell latency.

Junichi Koshiyama, Nobuyuki Yoshikawa

Anna Kidiyarova-Shevchenko, Alexander F. Kirichenko

Timur V. Filippov, M. Dorojevets, Anubhav Sahu +3 more

We have designed and demonstrated an Arithmetic-Logic Unit (ALU) based on RSFQ technology as a required step toward building an 8-bit RSFQ processor datapath. The circuit was designed and fabricated with HYPRES' standard 4.5 kA/cm2process. The target clock frequency of the ALU is 20 GHz. In this paper, we present the design and functionality (low-speed) test results of the 8-bit ALU.