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International nano letters.

A modular approach for testable conservative reversible multiplexer circuit for nano-electronic confine application

Nirupma Pathak, Santosh D. Kumar, Neeraj Kumar Misra, Bandan Kumar Bhoi

Published Oct 11, 2019• 11 citations
Publisher

Abstract

Abstract Quantum technology has an attractive application nowadays for its minimizing the energy dissipation, which is a prominent part of any system-level design. In this article, the significant module of a multiplexer, an extended ton:1 is framed with prominent application in the control unit of the processor. The proposed multiplexer modules are framed by the algorithm, which is extended perspective based. Further, quantum cost and gate count are less to ensure the efficient quantum computing framed. In addition, the QCA computing framework is an attempt to synthesize the optimal primitives in conservative reversible multiplexer in nano-electronic confine application. The developed lemmas is framed to prove the optimal parameters in the reversible circuit. Compared with existing state-of-art-works, the proposed modular multiplexer, the gate count, quantum cost and unit delay are optimal.

DOI
10.1007/s40089-019-00283-9

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Abstract Quantum technology has an attractive application nowadays for its minimizing the energy dissipation, which is a prominent part of any system-level design. In this article, the significant module of a multiplexer, an extended ton:1 is framed with prominent application in the control unit of the processor. The proposed multiplexer modules are framed by the algorithm, which is extended perspective based. Further, quantum cost and gate count are less to ensure the efficient quantum computing framed. In addition, the QCA computing framework is an attempt to synthesize the optimal primitives in conservative reversible multiplexer in nano-electronic confine application. The developed lemmas is framed to prove the optimal parameters in the reversible circuit. Compared with existing state-of-art-works, the proposed modular multiplexer, the gate count, quantum cost and unit delay are optimal.
Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architecture and arithmetic logic unit designs. We present an optimization method for reversible logic synthesis based on the Integrated Qubit (IQ) library. This method works in conjunction with existing methods to further improve quantum cost and delay of a synthesized reversible logic circuit. This algorithm runs in O(N) time, and reduces the quantum cost of synthesized circuit by up to 45 percent. In addition, the process of replacing the gates in the synthesized circuits with IQ gates uses a locally optimal technique whose major benefits include reduction of cost as well as delay.
Low power architectures are more pronounced for different applications that extend from Internet of Things to Quantum computing. Primitive combinational logic circuits induce from bit deletion due to information loss during the processing of input information which results in energy loss. The computations involving reversibility cancel the loss of information by sustaining the input bits from output. In the basic arithmetic and logic units, the combinational circuits play a significant role in determining the performance of the processor. The principles involved in the design of reversibility is an upcoming technology for ultra-low power applications. The reversible logic circuits furnish a thoroughly new way to progress in Quantum computing. In this article, we propose an energy tolerant low power reversible multiplexer with optimum energy loss. The proposed multiplexer also reduces the ancillae, garbage outputs and quantum cost considerably.
Quantum computing is one of the most significant anticipation towards the accomplishment of interminable consumer demands of small, high speed, and low-power operable electronics devices. As reversible logic circuits have direct applicability to quantum circuits, design and synthesis of these circuits are finding grounds for emerging nano-technologies of quantum computing. Multiple Controlled Toffoli (MCT) and Multiple Controlled Fredkin (MCF) are the fundamental reversible gates that playing key role in this phase of development. A number of special reversible gates have also been presented so far, which were claimed superior for providing certain purposes like logic development and testing. This paper critically analyses a range of these gates to procure an optimal solution for design, synthesis and testing of reversible circuits. The experimentation is facilitated at three subsequent levels, i.e. gates properties, quantum cost and design & testability. MCT and MCF gates are found up to 50% more cost-effective than special gates at design level and 34.4% at testability level. Maximum reversibility depth (MRD) is included as a new measurement parameter for comparison. Special gates exhibit MRD up to 7 which ideally should be 1 for a system to be physically reversible as that of MCT and MCF gates.
Reversible logic technology has the most promising role in quantum computing. With the evolution of high-performance computing devices, future processors are focusing on quantum technology for their development and fabrication. This work focuses on the development of a novel digital processor with memory via parity-preserving reversible logic gates and quantum cellular automaton (QCA). The design and realization of the integral components of the digital processor have been performed with reversible KMD gates. The processor’s main modules include the ALU, multipliers, floating-point division unit, control unit, and memory unit. It has a control unit to monitor and control the operation of the processor. The QCA design of individual modules of the developed processor is carried out with appropriate multilayer wire crossing. The performances of the individual models of the processor are compared and analyzed with those of existing designs. The reversible processor has 891 quantum costs, 141 constant inputs, and 188 garbage outputs; it needs 120 reversible gates and 1397 total costs. The results show that the developed processor modules are better than the existing modules, as the appropriate use of reversible logic gates for modern-day high-performance, economical and low-power-consumption processors.
The effects of quantum mechanics dominate nanoscale devices, where Moore’s law no longer holds true. Additionally, with the recent rapid development of quantum computers, the development of reversible gates to overcome the problems of energy and information loss and the nano-level quantum-dot cellular automata (QCA) technology to efficiently implement them are in the spotlight. In this study, a full adder-subtractor, a core operation of the arithmetic and logic unit (ALU), the most important hardware device in computer operations, is implemented as a circuit capable of reversible operation using QCA-based reversible gates. The proposed circuit consists of one reversible QCA gate and two Feynman gates and is designed as a multi-layer structure for efficient use of area and minimization of delay. The proposed circuit is tested on QCADesigner 2.0.3 and QCADesigner-E 2.2 and shows the best performance and lowest energy dissipation. In particular, it shows tremendous improvement rates of 180% and 562% in two representative standard design cost indicators compared to the best existing studies, and also shows the highest circuit average output polarization.
Quantum Computing is an emerging technology that offers significant advantages over classical computation with regard to speed, circuit density and heat dissipation. These future computers employs the reversibility property to make the computations faster. In contrast to conventional computers, quantum computers can restore the input bits uniquely after the logic block is evaluated, as input and output bits exhibits one-to-one correlation. To make the best use of this technology with existing limitations ,this paper focuses on building quantum adder circuits with less gate-count using IBM Qiskit. The Qiskit output should be analogous to the conventional output. Also to analyze the working of quantum circuits in layout structure, "Quantum Dot Cellular Automata(QCA)" technology is employed. In this approach, the reversible adder design is executed using the QCA designer tool with efficient formulation and novel arrangement of QCA cells. The proposed design has better complexity than other previous works with a declined number of gate-count, cell-count, delay and area.