Low power architectures are more pronounced for different applications that extend from Internet of Things to Quantum computing. Primitive combinational logic circuits induce from bit deletion due to information loss during the processing of input information which results in energy loss. The computations involving reversibility cancel the loss of information by sustaining the input bits from output. In the basic arithmetic and logic units, the combinational circuits play a significant role in determining the performance of the processor. The principles involved in the design of reversibility is an upcoming technology for ultra-low power applications. The reversible logic circuits furnish a thoroughly new way to progress in Quantum computing. In this article, we propose an energy tolerant low power reversible multiplexer with optimum energy loss. The proposed multiplexer also reduces the ancillae, garbage outputs and quantum cost considerably.
Low power architectures are more pronounced for different applications that extend from Internet of Things to Quantum computing. Primitive combinational logic circuits induce from bit deletion due to information loss during the processing of input information which results in energy loss. The computations involving reversibility cancel the loss of information by sustaining the input bits from output. In the basic arithmetic and logic units, the combinational circuits play a significant role in determining the performance of the processor. The principles involved in the design of reversibility is an upcoming technology for ultra-low power applications. The reversible logic circuits furnish a thoroughly new way to progress in Quantum computing. In this article, we propose an energy tolerant low power reversible multiplexer with optimum energy loss. The proposed multiplexer also reduces the ancillae, garbage outputs and quantum cost considerably.
To meet expectations of the futuristic technologies, thrust is on fast communication, low power, high computational speeds with delay intolerance. VLSI technology is laboring to meet the demands by incorporating low-power solutions to improve performance. Component size has come to Nano scales however, it has challenges of managing heat dissipation and physical limitations in fabrication. Reversible logic technology has gained momentum in research due to its prominence in Quantum computing and zero power dissipation. The arithmetic and Logic Unit is the significant component of any computing architecture, carrying out operations rigorously while consuming power for the endurance of performance. The proposed approach of designing the fault-tolerant Arithmetic and Logical Unit (ALU) in reversible logic for future computers. Analysis of the proposed design to existing designs is on the quantum cost (QC), garbage output (GO), ancilla input (AI), gate utilization (GC) and number of operations achieved. Improvements observed is at an average of 70% in AI and GC, 59% in QC , 53% in GO and operations are up by 33% to cater to the least power consumption applications.
Reversible computing has emerged as a promising solution for reducing energy dissipation in digital systems by addressing the fundamental limitations caused by information loss.Quaternary reversible logic, which uses multi-valued representations, provides higher information density, reduced interconnect complexity, and better scalability when compared to conventional binary logic.This work presents the design and implementation of a quaternary reversible Arithmetic Logic Unit (ALU) that integrates essential computational modules, including arithmetic units, logical units, memory units, decoders, and multiplexers.The proposed architecture supports efficient data routing and precise operation control through a scalable control unit and a selection-line-based design approach.The designed ALU demonstrates reduced quantum cost, fewer garbage outputs, and minimized constant inputs in comparison with existing reversible ALU designs, while remaining compatible with larger reversible and quantum computing architectures.Simulation results and comparative analysis validate the improved efficiency and low-power potential of the proposed system, making it suitable for next-generation computing applications.The complete design is implemented using Verilog HDL and synthesized and simulated using Xilinx Vivado Design Suite 2025.
Reversible computing is an emerging field of research and has made remarkable progress. Owing to the reduced energy dissipation in reversible circuits, a lot of research has been done on the design of reversible circuits. In reversible logic circuit designs, along with primary inputs, few constant inputs (Ancilla Inputs) are used to realize required reversible functions. In addition to this, few unused or extra output bits are generated; these bits are named as Garbage Output bits. A challenge in the reversible computation is to use minimum Ancilla Inputs and generate zero Garbage Outputs. In this work, we present designs for addition, subtraction, and addition or subtraction operations. The designs are primarily optimized to achieve zero Garbage Outputs and minimum Ancilla Inputs. In addition, these proposed arithmetic circuits are designed for best Gate Count and Quantum Cost values compared to the existing counterparts.
At present days , reversible logic circuits have many applications in the field of optical information processing, digital signal processing , nano technology and quantum computing . Reversible logic plays an important role when computations with minimum energy dissipation are considered. The purpose of designing reversible logic is to decrease the number of area, power, garbage outputs , constant inputs, quantum cost, reversible gates, delay and hardware complexity . This paper reveals a review on some reversible logic gates, which is useful in designing more complex systems having reversible circuits and can do execution of more complex operations using quantum computers. In upcoming days digital technology will be using reversible logic gates in order to reduce the propagation delay and power consumption as it provides negligible loss of information in the circuit. Keywords: Reversible Gate, Garbage output, quantum cost, Reversible logic, Power dissipation
Reversible logic plays a vital role in Quantum computing and Nanotechnology which in future can be applied for low power processor applications. In this paper, we propose, ultra area efficient reversible quantum multiplier based on Radix-2 Booth's recoding algorithm. The Non-Fault tolerant Radix-2 Booth's recoding architecture is designed and optimized for Quantum Cost and Garbage Outputs. The proposed methodology for reversible quantum multiplier shows the improvement in terms of Quantum Cost, Garbage Outputs and gates count compared to all the existing reversible quantum multiplier designs.
Reversible logic; transforms logic signal in a way that allows the original input signals to be recovered from the produced outputs, has attracted great attention because of its application in diverse areas such as quantum computing, low power computing, nanotechnology, DNA computing, quantum dot cellular automata, optical computing. In this paper, we design low power binary comparators using reversible logic gates. Firstly, single bit binary reversible comparator circuits are designed using different reversible gates along with proposed gate named Newly Proposed Gate. Then, these procedures are generalized for constructing binary n-bit reversible comparator circuit. The design synthesis consists of two parts: Comparator Cell and Propagator Cell. An algorithm, based on our proposed design, shows that proposed circuit reduces overall cost and it outperforms than existing sequential comparator circuits. Also, comparing with existing tree-based comparator circuit, proposed design reduces quantum cost, garbage output and gate count in a significance level which means better improvement as cost of any quantum circuit is directly associated with quantum cost, garbage output and gate count.