Reversible logic plays a vital role in Quantum computing and Nanotechnology which in future can be applied for low power processor applications. In this paper, we propose, ultra area efficient reversible quantum multiplier based on Radix-2 Booth's recoding algorithm. The Non-Fault tolerant Radix-2 Booth's recoding architecture is designed and optimized for Quantum Cost and Garbage Outputs. The proposed methodology for reversible quantum multiplier shows the improvement in terms of Quantum Cost, Garbage Outputs and gates count compared to all the existing reversible quantum multiplier designs.
Reversible logic plays a vital role in Quantum computing and Nanotechnology which in future can be applied for low power processor applications. In this paper, we propose, ultra area efficient reversible quantum multiplier based on Radix-2 Booth's recoding algorithm. The Non-Fault tolerant Radix-2 Booth's recoding architecture is designed and optimized for Quantum Cost and Garbage Outputs. The proposed methodology for reversible quantum multiplier shows the improvement in terms of Quantum Cost, Garbage Outputs and gates count compared to all the existing reversible quantum multiplier designs.
Quantum computation is modeled by quantum circuits. All the quantum operations are reversible so the quantum circuits can be built using reversible logic gates. Reversible computing is the emerging technology, its major role is in the field of quantum computing, optical computing, and design of low power nanocircuits. The most frequently used computational unit for digital signal processing and multimedia applications is multiplier. To compute square of an operand, regular multipliers are used in general. This paper proposes a dedicated quantum circuit for computing square of an operand efficiently compared to the existing multipliers in the literature. The squaring unit is mathematically modeled and its metrics quantum cost, garbage outputs and ancilla input, gate count are calculated. We compared the proposed design with the existing multipliers to compute square and found that proposed square unit is efficient in terms of quantum cost, garbage outputs, ancilla inputs and gate count. The proposed reversible square circuit has 63% to 85% improvement of quantum cost, garbage outputs, ancilla inputs and gate count over existing reversible multiplier circuits.
Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing, DNA computing, bioinformatics, and nanotechnology. This paper presents two new 4 × 4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n × n bit multipliers. An implementation of reversible HNG is also presented. This implementation shows that the full adder design using HNG is one of the best designs in term of quantum cost. An implementation of MKG is also presented in order to have a fair comparison between our proposed reversible multiplier designs and the existing counterparts. The proposed reversible multipliers are optimized in terms of quantum cost, number of constant inputs, number of garbage outputs and hardware complexity. They can be used to construct more complex systems in nanotechnology.
Reversible logic, by enabling computations without loss of information, offers a promising approach to significantly reducing energy dissipation, making it a key technology for low-power and quantum computing systems. Parity-preserving reversible circuits further enhance reliability, enabling fault detection in nanoscale systems. Multiplication, a fundamental operation in computing and signal processing, benefits significantly from efficient reversible designs. However, existing reversible Vedic multipliers often suffer from excessive Quantum Cost (QC), Garbage Outputs (GO), and Constant Inputs (CI). This paper proposes two new 2-bit parity-preserving reversible quantum Vedic multipliers, serving as the foundational block for scalable n-bit multipliers, that are enhanced to reduce quantum metrics without compromising performance. The proposed circuits are simulated using the Quirk tool to test their correct functionality. Comparative analysis shows that the best proposed design outperforms existing architectures on average by 34%, 53%, and 9% in constant inputs, garbage outputs, and quantum cost, respectively, providing a fault-tolerant, cost-efficient, and scalable solution for next-generation quantum computing systems.
Low power architectures are more pronounced for different applications that extend from Internet of Things to Quantum computing. Primitive combinational logic circuits induce from bit deletion due to information loss during the processing of input information which results in energy loss. The computations involving reversibility cancel the loss of information by sustaining the input bits from output. In the basic arithmetic and logic units, the combinational circuits play a significant role in determining the performance of the processor. The principles involved in the design of reversibility is an upcoming technology for ultra-low power applications. The reversible logic circuits furnish a thoroughly new way to progress in Quantum computing. In this article, we propose an energy tolerant low power reversible multiplexer with optimum energy loss. The proposed multiplexer also reduces the ancillae, garbage outputs and quantum cost considerably.
Reversible logic has emerged as a promising computing paradigm having applications in quantum computing, optical computing, dissipation less computing and low power computing etc. In reversible logic there exists a one to one mapping between the input and output vectors. Reversible circuits require constant ancilla inputs for reconfiguration of gate functions and garbage outputs that help in keeping reversibility. Quantum circuits of many qubits are extremely difficult to realize thus reduction in the number of ancilla inputs and the garbage outputs is the primary goal of optimization. In existing literature researchers have proposed several designs of reversible quantum multipliers based on reversible full adders and reversible half adders. The use of reversible full adders and the half adders for the addition of partial products increases the overhead in terms of number of ancilla inputs and number of garbage outputs. This paper presents a binary tree based design methodology for a NxN reversible quantum multiplier. The proposed binary tree based design methodology for NxN reversible quantum multiplier performs the addition of partial products in parallel using the reversible ripple quantum adders with no garbage output and ancilla bit, thereby minimizing the number of ancilla and garbage bits used in the design. The proposed design methodology shows the improvement of 17.86% to 60.34% in terms of ancilla inputs; and 21.43% to 52.17% in terms of garbage outputs compared to all the existing reversible quantum multiplier designs.
A reversible logic has application in quantum computing. A reversible logic design needs resources such as ancilla and garbage qubits to reconfigure circuit functions or gate functions. The removal of garbage qubits and ancilla qubits are essential in designing an efficient quantum circuit. In the literature, there are multiple designs that have been proposed for a reversible multiplication operation. A multiplication hardware is essential for the circuit design of quantum algorithms, quantum cryptanalysis, and digital signal processing (DSP) applications. The existing designs of reversible quantum integer multipliers suffer from redundant garbage qubits. In this work, we propose a reversible logic based, garbage-free and ancilla qubit optimized design of a quantum integer multiplier. The proposed quantum integer multiplier utilizes a novel add and rotate methodology that is specially suitable for a reversible computing paradigm. The proposed design methodology is the modified version of a conventional shift and add method. The proposed design of the quantum integer multiplier incorporates add or no operation based on multiplier qubits and followed by a rotate right operation. The proposed design of the quantum integer multiplier produces zero garbage qubits and shows an improvement ranging from 60% to 90% in ancilla qubits count over the existing work on reversible quantum integer multipliers.