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Journal of Optical Communications

Influence of Loading, Regeneration and Recalling Elements Processes on the System Behavior of All Optical Data Bus Line System Random Access Memory

Iraj Sadegh Amiri, Ahmed Nabih Zaki Rashed, Abd El–Naser A. Mohammed, Walid Fawzy Zaky

Published Aug 15, 2019• 78 citations
Publisher

Abstract

Abstract The most powerful computer is in a very big need for a reliable random access memory (RAM) which can buffer digital data in. All optical RAM design is introduced in three phases. Those are the loading process phase which describes how data will be entering the closed trap from the line bus. The regeneration process phase which describes how data trapped are regenerated to not to lose its power or get a distortion. As well as the recalling process which describes how trapped data be handled to the line bus is also introduced.

DOI
10.1515/joc-2019-0163

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Superconductor electronics offers logic circuits for high-speed data processing and high-performance computing. The main barrier to practical application is the lack of high-speed and low-power memory. It is widely believed that the most reliable and functional bit cell for superconducting memory is the vortex transitional bit cell, which was successfully used by Nagasawa in a 4-kb memory. This paper reviews existing challenges in this type of Josephson memory devices and discusses engineering issues in implementing a model single flux quantum random access memory. We evaluate the contributions that various components of the memory system make to delay and power dissipation. The 256-bit memory provides an experimentally confirmed read access time of 190 ps. As a result, we found that delay and power dissipation are found largely in the address decoder, line drivers, bit-selection scheme, and the data readout circuitry. With these circuits being similar for various magnetic memory devices, our findings provide essential data for a comprehensive assessment of new concepts for bit cells, readout, and write in superconducting memories.
We designed a superconducting random access memory (RAM) in which all component circuits can be operated with dc-bias currents. A dc-powered superconducting loop driver and a dc-powered sense circuit are effectively combined with single flux quantum (SFQ) circuits. We proposed a pipeline structure for the memory cell array composed of the dc-powered loop drivers, the dc-powered sense circuits, passive transmission lines (PTLs), and SFQ gates. This pipeline structure enables a clock operation of 10 GHz even in a large-scale RAM. An effective device structure for the RAM based on a planarized multi-layer device structure was proposed. A dc-power layer and two PTL layers were placed under the ground plane. This structure is indispensable to create the pipeline structure using PTLs. The large inductance formed in the power layer enables low power dissipation of the RAM. We found from the estimations that 10 GHz clock operation with extremely low power dissipation can be achieved even in a large-scale RAM of 1 Mbit.