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IPSJ Transactions on System and LSI Design Methodology

Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses

Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi

Published Jan 1, 2019• 4 citations
Publisher

Abstract

A conversion method of a netlist consisting of conventional logic gates for superconducting rapid single flux quantum (RSFQ) circuit realization is proposed. The method detects OR gates which can be replaced with confluence buffers (CBs) which converge their input pulses into their outputs. The detection problem of replaceable OR gates is treated as a SAT problem. Each OR gate requires clock input in RSFQ circuits. By replacing OR gates with CBs, wiring for clocking those OR gates are eliminated and the number of active devices known as Josephson junctions is reduced.

DOI
10.2197/ipsjtsldm.12.78

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A conversion method of a netlist consisting of conventional logic gates for superconducting rapid single flux quantum (RSFQ) circuit realization is proposed. The method detects OR gates which can be replaced with confluence buffers (CBs) which converge their input pulses into their outputs. The detection problem of replaceable OR gates is treated as a SAT problem. Each OR gate requires clock input in RSFQ circuits. By replacing OR gates with CBs, wiring for clocking those OR gates are eliminated and the number of active devices known as Josephson junctions is reduced.
Among the major issues in modern large-scale rapid single-flux quantum (RSFQ) circuits are the complexity of the clock network, tight timing tolerances, poor applicability of existing CMOS-based design algorithms, and extremely deep pipelines, which reduce the effective clock frequency. In this article, asynchronous dynamic single-flux quantum majority gates are proposed to solve some of these problems. The proposed logic gates exhibit high bias margins and do not require significant area or a large number of Josephson junctions as compared to existing RSFQ logic gates. These gates exhibit a tradeoff among the input skew tolerance, clock frequency, and bias margins. Asynchronous logic gates greatly reduce the complexity of the clock network in large-scale RSFQ circuits, thereby alleviating certain timing issues and reducing the required bias currents. Furthermore, asynchronous logic allows existing design algorithms to utilize CMOS approaches for synthesis, verification, and testability. The adoption of majority logic in complex RSFQ circuits also reduces the pipeline depth, enabling higher clock speeds in very large scale integration RSFQ circuits.
Some basic cells in the rapid single-flux quantum (RSFQ) family of superconductive logic circuits were studied. An input stage, a buffer, and an OR gate were simulated and laid out for a standard niobium-based fabrication process. The resulting circuits perform properly for clock speeds up to 1 GHz. For the simpler circuits tested, the measured margins are wide, consistent with simulations, and not very dependent on clock speed. However, margin decreases with increased circuit complexity. The input stage converts a rising edge into an SFQ pulse, which has a small amplitude and narrow width in time. On the present circuits, these pulses are about 200 mu V in amplitude and 10 ps in width. To facilitate measurement, the authors have chosen as the output an asymmetrical superconducting quantum interference device (SQUID) consisting of two Josephson junctions. It converts SFQ pulses into 2.5 mV latching output levels on chip. By inductively coupling SFQ pulses into the SQUID loop, DC current isolation between the RSFQ circuit-under-test and the output stage is provided. The SQUID was optimized for 2 GHz operations.>
Rapid single flux quantum (RSFQ) logic needs synchronous pulses for each gate, so the clock-wiring problem is more serious when designing larger scale circuits with this logic. So we have proposed a new SFQ logic which follows Boolean algebra perfectly by using set and reset pulses. With this logic, the level information of current input is transmitted with these pulses generated by level-to-pulse converters, and each gate calculates logic using its phase level made by these pulses. Therefore, our logic needs no clock in each gate. We called this logic `Boolean SFQ (BSFQ) logic'. In this paper, we report design and experimentation for an AND gate with inverting input based on BSFQ logic. The experimental results for OR and XOR gates are also reported.
The Rapid Single-Flux-Quantum logic (RSFQ) presents an efficient way to achieve ultra fast digital operations. This logic uses the macroscopic effects which can be found in nano-structured superconductor devices such as the Josephson AC and DC effects, and the magnetic flux quantization. As the typical time of the Josephson junction quantized phase leap 2π is in the order of picoseconds, the RSFQ circuits can operate with clock frequencies in the order of hundreds of GHz. This invited paper focuses on basic principles of superconducting RSFQ logic as well as on typical applications, such as the signal conversion or petaflops computing systems. In addition we point out the benefits of the semi-metallic NbN-TaxN-NbN Josephson junction technology, which has been developed at CEA-INAC in Grenoble.
A new family of dc-powered Josephson junction digital devices, the Rapid Single Flux Quantum (RSFQ) logic, is described. The devices use overdamped Josephson junctions and two-junction interferometers to store, pass and process the digital information presented in form of single flux quanta. We have carried out extensive numerical simulation of the dynamics of the RSFQ logic gates and of some more complex circuits including serial full adder and reversible shift register, within the standard microscopic-theory ("Werthamer") description of Josephson junctions. The minimum clock cycles of the basic RSFQ circuits turn out to be as small as 2.5 ps. The most promising ways to use the RSFQ logic circuits at the present stage of development of the Josephson junction digital technology are discussed.
This paper presents a basic circuit concept for pulse-driven asynchronous circuits using superconducting rapid single-flux-quantum (RSFQ) logic gates. Today's computer systems perform using a synchronous clock distributed over the whole system. The distribution of the clock signal becomes more difficult as the clock frequency increases because the wavelength of the clock signal becomes shorter than the system size. One way to solve this problem is to use asynchronous circuits in which all circuits perform their functions only under the law of cause and effect. We propose an implementation of the basic asynchronous circuit performing OR/AND logic operations between SFQ pulses. The operations are confirmed by SPICE simulation. We will show a design method for combinational circuits using the proposed basic circuits.