Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Bulletin of the American Physical Society

Measuring and Suppressing Error Correlations in Quantum Circuits

Claire Edmunds, Cornelius Hempel, Sandeep Mavadia, Harrison Ball, Robert J. Harris, Virginia Frey, Thomas M. Stace, Michael J. Biercuk

Published Mar 5, 2018• 0 citations
OpenAlex

Related papers

Dynamically corrected gates suppressing spatiotemporal error correlations as measured by randomized benchmarking

Claire Edmunds, Cornelius Hempel, R. J. Harris +3 more

This work introduces a method to measure error correlations in quantum circuits, both temporally between gates and spatially between qubits. The authors demonstrate that using appropriately tailored dynamically corrected gates can not only reduce the likelihood of errors, but also correlations between them, and can hence be used to precondition a circuit for quantum error correction.

arXiv:1909.10727•Physical Review Research•Feb 13, 2020•28 citations

Coding and Correcting Circuits for Two-Quantum Errors

吕洪君 Lü Hongjun, 解光军 Xie Guangjun

Acta Optica Sinica•Jan 1, 2011•0 citations

Demonstration of Logical Error Suppression in a Surface Code Memory on a Cloud-Accessible IBM Superconducting Processor

Shuwen Kan, Aaron Hoyt, Sean Garner +8 more

Quantum error correction can suppress logical errors exponentially with code distance when physical noise is below threshold. Realizing this on hardware requires tight coordination among quantum gates, mid-circuit measurements, and qubit coherence. Device variation, noise asymmetry, and correlations across space and time complicate the translation of these capabilities into logical error suppression. Here, we study rotated surface-code memory on an IBM Nighthawk r2 processor. Performance varies across tested processor placements, which we attribute to differences in qubit quality. We optimize the code by combining short readout, fused measurement and reset, and an XX echo on data qubits during ancilla readout. Compared with standard readout without reset or echo, the optimized syndrome extraction circuit reduces the median per-round logical error rate by factors of 3.8 in the X basis and 1.4 in the Z basis. In memory experiments of up to 150 rounds, the distance advantage weakens, alongside long-lived correlations that may reflect a persistent error component. Under our optimization recipe, increasing the protected distance from 3 to 6 while holding the other distance fixed reduces the per-round logical error rate from 0.53% to 0.24% in Z memory and from 0.52% to 0.22% in X memory. The corresponding error-suppression factors under maximum-likelihood decoding are 1.68 and 1.85. These results connect circuit compilation and optimization to surface-code memory performance and limitations, and motivate QPU and QEC circuit codesign for fault-tolerant quantum computing primitives on current cloud hardware.

quant-pharXiv:2610.23840•Oct 19, 2026•0 citations

Measuring and Suppressing Error Correlations in Quantum Circuits

Claire Edmunds, Cornelius Hempel, R. Harris +4 more

Quantum error correction provides a path to large-scale quantum computers, but is built on challenging assumptions about the characteristics of the underlying errors. In particular, the mathematical assumption of independent errors in quantum logic operations is at odds with realistic environments where error-sources may exhibit strong temporal correlations. We present experiments enabling the identification of error correlations between operations in quantum circuits, using only projective measurements at the end of the circuit. Using a single trapped ion qubit and engineered noise with tunable temporal correlations, we identify a clear signature of error correlations between sequential gates in randomly composed quantum circuits, and extract quantitative measures linked to the underlying noise correlation length. By replacing all gates in these circuits with "virtual" dynamically corrected gates (DCGs), we demonstrate that even in the presence of strongly correlated noise the signatures of error correlations between sequential gates appear similar to standard gates exposed to uncorrelated noise. A theoretical model applied to our experiments reveals that common DCGs suppress the correlated error component by over $270\times$ with $95\%$ confidence. Using block-correlated noise, we explore the scaling of the effective error correlation length at the virtual level, and show that DCGs exhibit error correlations indistinguishable from those arising from uncorrelated noise.

arXiv:1712.04954•Dec 13, 2017•5 citations

General error mitigation for quantum circuits

Manpreet Singh Jattana, Fengping Jin, Hans A. De Raedt +1 more

•Jan 1, 2020•4 citations

Foundations of quantum error correction

Wen-Ching Li

AMS/IP studies in advanced mathematics•Jul 20, 2007•4 citations
Quantum error correction can suppress logical errors exponentially with code distance when physical noise is below threshold. Realizing this on hardware requires tight coordination among quantum gates, mid-circuit measurements, and qubit coherence. Device variation, noise asymmetry, and correlations across space and time complicate the translation of these capabilities into logical error suppression. Here, we study rotated surface-code memory on an IBM Nighthawk r2 processor. Performance varies across tested processor placements, which we attribute to differences in qubit quality. We optimize the code by combining short readout, fused measurement and reset, and an XX echo on data qubits during ancilla readout. Compared with standard readout without reset or echo, the optimized syndrome extraction circuit reduces the median per-round logical error rate by factors of 3.8 in the X basis and 1.4 in the Z basis. In memory experiments of up to 150 rounds, the distance advantage weakens, alongside long-lived correlations that may reflect a persistent error component. Under our optimization recipe, increasing the protected distance from 3 to 6 while holding the other distance fixed reduces the per-round logical error rate from 0.53% to 0.24% in Z memory and from 0.52% to 0.22% in X memory. The corresponding error-suppression factors under maximum-likelihood decoding are 1.68 and 1.85. These results connect circuit compilation and optimization to surface-code memory performance and limitations, and motivate QPU and QEC circuit codesign for fault-tolerant quantum computing primitives on current cloud hardware.
Quantum error correction provides a path to large-scale quantum computers, but is built on challenging assumptions about the characteristics of the underlying errors. In particular, the mathematical assumption of independent errors in quantum logic operations is at odds with realistic environments where error-sources may exhibit strong temporal correlations. We present experiments enabling the identification of error correlations between operations in quantum circuits, using only projective measurements at the end of the circuit. Using a single trapped ion qubit and engineered noise with tunable temporal correlations, we identify a clear signature of error correlations between sequential gates in randomly composed quantum circuits, and extract quantitative measures linked to the underlying noise correlation length. By replacing all gates in these circuits with "virtual" dynamically corrected gates (DCGs), we demonstrate that even in the presence of strongly correlated noise the signatures of error correlations between sequential gates appear similar to standard gates exposed to uncorrelated noise. A theoretical model applied to our experiments reveals that common DCGs suppress the correlated error component by over 270×270\times270× with 95%95\%95% confidence. Using block-correlated noise, we explore the scaling of the effective error correlation length at the virtual level, and show that DCGs exhibit error correlations indistinguishable from those arising from uncorrelated noise.