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IEICE Technical Report; IEICE Tech. Rep.

Design of SFQ Floating-Point Units Using Nb Advanced Process

Toshiki Kainuma, Yasuhiro Shimamura, Fumishige Miyaoka, Yuki Yamanashi, Yoshikawa Nobuyuki, Fujimaki Akira, Takagi Naofumi, Kazuyoshi Takagi

Published Oct 13, 2009• 0 citations
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Recently, we proposed a new data-path architecture, named a large-scale reconfigurable data-path (LSRDP), based on single-flux-quantum (SFQ) circuits, to establish a fundamental technology for future high-end computers. In this architecture, a large number of SFQ floating-point units (FPUs) are used as core components, and their high performance and low power consumption are essential. In this research, we implemented an SFQ half-precision bit-serial floating-point multiplier (FPM) with a target clock frequency of 50GHz, using the AIST 10kA/cm2 Nb process. The FPM was designed, based on a systolic-array architecture. It contains 11,066 Josephson junctions, including on-chip high-speed test circuits. The size and power consumption of the FPM are 6.66mm × 1.92mm and 2.83mW, respectively. Its correct operation was confirmed at a maximum frequency of 93.4GHz for the exponent part and of 72.0GHz for the significand part by on-chip high-speed tests.

IEICE Transactions on Electronics•Jan 1, 2014•13 citations
We have been developing the floating-point unit (FPU) based on single-flux-quantum (SFQ) logic toward a highspeed and low-power superconducting graphical processing unit. The floating-point divider is the most complicated circuit element of the SFQ FPU. We designed the SFQ floating-point divider on the basis of Goldschmidt's algorithm, which is one of multiplicative hardware algorithms for division. Because the multiplies in the divider can be used for multiplication in the FPU by employing the multiplicative division algorithm, the FPU can be efficiently designed by using the designed floating-point divider. We show the circuit scale estimation of the FPU that uses the designed divider as a function on floating-point precision. We measured the 4-bit and 11-bit SFQ floating-point dividers implemented by the AIST 10 kA/cm2Nb advanced process. The 11-bit SFQ floating- point divider is composed of 8091 Josephson junctions and can be applied to half-precision FPU. We confirmed correct operation of the 4-bit SFQ divider by low-frequency function test.
Recently, we proposed a new data-path architecture, named a large-scale reconfigurable data-path (LSRDP), based on single-flux-quantum (SFQ) circuits, to establish a fundamental technology for future high-end computers. In this architecture, a large number of SFQ floating-point units (FPUs) are used as core components, and their high performance and low power consumption are essential. In this research, we implemented an SFQ half-precision bit-serial floating-point multiplier (FPM) with a target clock frequency of 50GHz, using the AIST 10kA/cm2 Nb process. The FPM was designed, based on a systolic-array architecture. It contains 11,066 Josephson junctions, including on-chip high-speed test circuits. The size and power consumption of the FPM are 6.66mm × 1.92mm and 2.83mW, respectively. Its correct operation was confirmed at a maximum frequency of 93.4GHz for the exponent part and of 72.0GHz for the significand part by on-chip high-speed tests.