60-GHz demonstration of an SFQ half-precision bit-serial floating-point adder using 10 kA/cm2 Nb process
T. Kato, Yuki Yamanashi, Nobuyuki Yoshikawa +4 more
We are developing a large-scale reconfigurable data-path (LSRDP) based on single-flux-quantum (SFQ) circuits to establish a fundamental technology for future high-performance computing systems. In the LSRDP, an SFQ floating-point adder (FPA) is one of the main and most complicated circuit blocks. In our previous study, we implemented an SFQ half-precision (16-bit) bit-serial FPA using the ISTEC 2.5 kA/cm2standard process, and demonstrated the correct operations at 24 GHz by on-chip high-speed tests. In this study, we designed and implemented an SFQ half-precision bit-serial FPA using a cell library for the AIST 10 kA/cm2Nb nine-metal-layer process (ADP2), and carried out on-chip high speed tests. The designed FPA contains 9661 Josephson junctions and occupies a circuit area of 12.95 mm2. Its target operation frequency is 50 GHz. We have demonstrated the correct operation of the FPA at the maximum frequency of 62 GHz although there is a functional error in the design. The measured DC bias margin ranges from 102% to 108% at 50 GHz operation. The total power consumption is measured to be 2.9 mW.
IEEE International Superconductive Electronics Conference (ISEC)•Jul 1, 2013•18 citations