Scalable FPGA-based qubit control hardware

Mats O. Tholén, Riccardo Borgani, Shan W. Jolin +1 more

Zhan Wang, Hai Yang Yu, Rongli Liu +7 more

We have developed an electronic hardware system for the control and readout of multi-superconducting qubit devices. The hardware system is based on the design ideas of good scalability, high synchronization and low latency. The system, housed inside a VPX-6U chassis, includes multiple arbitrary-waveform generator (AWG) channels, analog-digital-converter (ADC) channels as well as direct current source channels. The system can be used for the control and readout of up to twelve superconducting transmon qubits in one chassis, and control and readout of more and more qubit can be carried out by interconnecting the chassis. By using field programmable gate array (FPGA) processors, the system incorporates three features that are specifically useful for superconducting qubit research. Firstly, qubit signals can be processed using the on-board FPGA after being acquired by ADCs, significantly reducing data processing time and data amount for storage and transmission. Secondly, different output modes, such as direct output and sequential output modes, of AWG can be implemented with pre-encoded FPGA. Thirdly, with data acquisition ADCs and controlAWGs jointly controlled by the same FPGA, the feedback latency can be reduced, and in ourtest a 178.4 ns latency time is realized. This is very useful for future quantum feedback experiments. Finally, we demonstrate the functionality of the system by applying the system to the control and readout of a 10 qubit superconducting quantum processor.

Pradeep Kumar Gautam, Shantharam Kalipatnapu, H Shankaranarayanan +4 more

Measuring a qubit state is a fundamental but error-prone task in quantum computing. As the number of qubits increases, scalable readout demands multiplexed qubit measurement, which often suffers from crosstalk and other nonidealities. The conventional approach of qubit state detection often struggles with scalability and noise resilience. Neural network (NN)-based discriminators have emerged as a promising alternative, offering superior performance for inferring qubit states from multiplexed signals. However, their deployment on hardware platforms like Field programmable gate arrays (FPGA) is hindered by computation complexity, resource constraints, and latency. In this work, we present an end-to-end methodology for designing and deploying quantized NN-based multi-qubit state discriminators on FPGAs. We demonstrate that implementing a fully connected neural network accelerator for multi-qubit readout is advantageous, balancing computational complexity with low latency requirements without significant loss in accuracy. We significantly reduce the FPGA footprint and latency of the neural network by employing quantization-aware training (QAT) to quantize weights, activations, and inputs, and leveraging automated mapping flows for efficient, hardware-aware design-space exploration and optimization. The hardware accelerator performs frequency-multiplexed readout of five superconducting qubits in 26.7 ns, on a radio frequency system on chip (RFSoC) ZCU111 FPGA. These modules can be implemented and integrated into existing FPGA based quantum control and readout platforms, making them ready for experimental deployment.

Unpil Baek, Yilun Xu, Gang Huang +2 more

Mathieu Toubeix, Èric Guthmuller, Adrian Evans +2 more

As scaling becomes a key issue for large-scale quantum computing, hardware control systems will become increasingly costly in resources. This article presents a compact direct digital synthesis architecture for signal generation adapted for spin qubits that is scalable in terms of waveform accuracy and the number of synchronized channels. The architecture can produce programmable combinations of ramps, frequency combs, and arbitrary waveform generation (AWG) at 5 GS/s, with a worst-case digital feedback latency of 76.8 ns. The field-programmable gate array (FPGA)-based system is highly configurable and takes advantage of bitstream switching to achieve the high flexibility required for scalable calibration. The architecture also provides GHz rate, multiplexed, in-phase and quadrature component, single-side band modulation for scalable reflectometry. This architecture has been validated in hardware on a Xilinx ZCU111 FPGA demonstrating the mixing of complex signals and the quality of the frequency comb generation for multiplexed control and measurement. The key benefits of this design are the increase of controllability of ramps at the digital-to-analog converter (DAC) frequency and the reduction in memory requirements by several orders of magnitude compared with existing AWG-based architectures. The hardware for a single channel is very compact, 2% of ZCU111 logic resources for one DAC lane in the default configuration, leaving significant circuit resources for integrated feedback, calibration, and quantum error correction.

Madiha Khalid, Umar Mujahid, Atif Raza Jafri +2 more