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IEICE Technical Report; IEICE Tech. Rep.

Equivalence Checking Method of Timed Logic Formulae for Design Verification of Single-Flux Quantum Circuits

Takahiro Kawaguchi, Kazuyoshi Takagi, Takagi Naofumi

Published Feb 28, 2012• 0 citations
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•Jan 1, 1997•0 citations
The semiconductor industry standard computer-aided-design (CAD) tool Cadence has been calibrated for a 3 /spl mu/m Niobium technology in order to design and build superconductive single flux quantum (SFQ) circuits. The top-down design methodology includes Verilog functional simulation, schematic capture, graphic layout, functional verification, design rule checking, electrical rule checking, and layout-vs.-schematic verification. This design framework has been used successfully at the University of Rochester in designing more than 15 elementary SFQ cells and three large scale digital and mixed-signal SFQ circuits, demonstrating significant improvement in both design efficiency and accuracy.
We present the design and results of experimental verification methods for ultra-low-power digital circuits based on the recently introduced energy-efficient single flux quantum (eSFQ) logic. Similar to another low-power SFQ logic, ERSFQ, eSFQ circuits make use of superconducting dc bias current dividers and thus avoid static power dissipation. As a result, per-gate power dissipation is reduced by two orders of magnitude as compared to conventional rapid single flux quantum and static power dissipation is zero. The eSFQ circuits are fabricated using the HYPRES standard 4.5 kA/cm2process. We integrate a low-pass analog-to-digital modulator with our eSFQ deserializer to enable testing at high speed. In this paper, we demonstrate the viability and performance metrics of eSFQ circuits through functional and high-speed tests. Specifically, we confirmed correct operation and present measured parameter margins.
The semiconductor industry standard compu- ter-aided-des~gn (CAD) tool Cadence has been calibrated for a 3 pm Niobium technology in order to design and build superconductive single flux quantum (SFQ) circuits. The top-down design methodology includes Verilog func- tional simulation, schematic capture, graphic layout, func- cation, design rule checking, electrical rule checking, and layout-vs.-schematic verification. This de- sign framework has been used successfully at the Univer- sity of Rochester in designing more than 15 elementary SFQ cells and three large scale digital and mixed-signal SFQ circuits, de onstrating significant improvement in both design efficiency and accuracy.