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IEEE Transactions on Applied Superconductivity

Development of an All-SFQ Superconducting Field-Programmable Gate Array

Calvin Christopher Maree, Coenrad Johann Fourie

Published Dec 11, 2018• 4 citations
Publisher

Abstract

Recent advances in fabrication complexity and density-especially for the Institute of Advanced Industrial Science and Technology (AIST) advanced process 2 (ADP2) process and the MIT Lincoln Lab (MITLL) SFQ5ee process and beyond-allow the implementation of a superconducting field-programmable gate array (SFPGA) with sufficient complexity to host a number of different programmed functions. We discuss design choices for an all single flux quantum SFPGA targeting these modern processes, making heavy use of passive transmission line (PTL) layers they provide. Various configurations for lookup tables, basic logic elements and timing schemes are shown, and a viable switch block implementation is discussed. Academic FPGA electronic design automation (EDA) tools are repurposed for mapping Verilog hardware description language (HDL) functions to the chosen SFPGA design, whilst HDL and electrical simulations are used to show its correct operation. We show simulations for programming and the operation of an SFPGA, and discuss die size requirements for practical implementation.

DOI
10.1109/tasc.2018.2886208

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Recent advances in fabrication complexity and density-especially for the Institute of Advanced Industrial Science and Technology (AIST) advanced process 2 (ADP2) process and the MIT Lincoln Lab (MITLL) SFQ5ee process and beyond-allow the implementation of a superconducting field-programmable gate array (SFPGA) with sufficient complexity to host a number of different programmed functions. We discuss design choices for an all single flux quantum SFPGA targeting these modern processes, making heavy use of passive transmission line (PTL) layers they provide. Various configurations for lookup tables, basic logic elements and timing schemes are shown, and a viable switch block implementation is discussed. Academic FPGA electronic design automation (EDA) tools are repurposed for mapping Verilog hardware description language (HDL) functions to the chosen SFPGA design, whilst HDL and electrical simulations are used to show its correct operation. We show simulations for programming and the operation of an SFPGA, and discuss die size requirements for practical implementation.
Field-programmable gate arrays (FPGAs) allow circuit reconfiguration in the field, which adds to the flexibility of electronic systems. Applied to superconductive electronics, reprogrammability allows system functionality to be changed without remanufacturing the circuit or dismantling a cryogenic setup. We discuss the design issues relevant to a superconducting programmable gate array (SPGA), and report an elementary 4200-junction SPGA. The SPGA is built around interconnected 2-input logic blocks which contain 4-bit lookup tables. Designs for the programming frame, address decoding, lookup tables and switch implementations are discussed, together with design constraints imposed by the unidirectional nature and large size of single flux quantum (SFQ) transmission lines.
Field-programmable gate arrays (FPGAs) provide a significantly cheaper solution for various applications in traditional semiconductor electronics. Single flux quantum (SFQ) technologies are developing rapidly and the availability of SFQ-specific FPGA will be very useful. Towards developing such an SFQ-specific FPGA, new designs of FPGA subcircuits for both synchronous and asynchronous operation of SFQ circuits are presented in this paper. Magnetic Josephson junctions (MJJs) are used as bias limiting junctions in energy-efficient rapid SFQ (ERSFQ) biasing to implement programmable switches in various subcircuits of the proposed FPGA fabric. Designs of all FPGA subcircuits are developed and are verified through circuit simulation. Verilog hardware description language (HDL) models are also developed for all FPGA circuit blocks to facilitate large-scale FPGA simulations for the implementation of the desired circuit on the proposed FPGA fabric. Designs of a few subcircuits with switches based on nondestructive readout cell are also given in the current paper for better comparison with MJJ switch based counterparts. Programming of MJJ-based switches is based on the ability to control the critical current of MJJs externally. Recent implementations of SFQ decoder is proposed for accessing individual MJJs through the current lines in a crossbar structure. Estimations for the area and power consumption are much better in comparison to previous attempts at designing an SFQ specific FPGA.
Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient, high- performance information processing systems because it has significantly low power consumption due to the adiabatic switching of Josephson junctions. We are developing a high-performance field-programmable gate array (FPGA) using superconducting AQFP circuits to reduce its energy consumption. The all-AQFP FPGA consists of logic blocks, switch blocks, connection blocks, and memory using AQFP circuits. In particular, the memory is composed of AQFP buffer chains, enabling high-density and low-power memory. The switch blocks can perform data routing as well as several logic functions, including majority,and, andorfunctions, which increases the design flexibility of the all-AQFP FPGA. We fabricated a one-unit all-AQFP FPGA and demonstrated its reconfigurable operation at low speed. It was found that much lower power consumption can be achieved in the new FPGA than in the other superconducting FPGAs.
Exascale computing and its associated increasingly massive amounts of data require increasingly efficient computing platforms; and semiconductor technology is struggling to keep up. Meanwhile, superconducting electronics (SCE) is increasingly gaining interest in both industry and academia as a serious contender to replace silicon for supercomputing. In particular, nonresistively biased single-flux quantum (SFQ) circuits have a theoretical potential of three orders of magnitude reduction in power accompanied with one order of magnitude of higher speed, and adiabatic quantum-flux-parametron (AQFP) circuits possess a theoretical potential of six orders of magnitude reduction in power when compared to the state-of-the-art semiconductor circuits. Unfortunately, the SCE community lacks a reliable design flow. Rather than creating a complete design flow from scratch, it is often more efficient to reuse well-established semiconductor tool flows developed by EDA companies that have benefited from research and development over the past half-century. One of the components of this flow is the hardware description language (HDL) modeling of gates for behavioral and functional simulation of large netlists. The previous HDL models proposed for SCE lack modularity are not compatible with existing CMOS standards, and are overly complex. This article presents SystemVerilog models for SFQ and AQFP gates and the circuits that interface between them. Our models are compatible with standard delay format and commercial simulators. They offer a generalizable modular debugging platform, are elegant and conceptual, and can capture many circuit parameters, environmental effects, and advanced SCE phenomena.
Single Flux Quantum (SFQ) electronic circuits originated with the advent of Rapid Single Flux Quantum (RSFQ) logic in 1985 and have since evolved to include more energy-efficient technologies such as ERSFQ and eSFQ. SFQ logic circuits, based on the manipulation of quantized flux pulses, have been demonstrated to run at clock speeds in excess of 120 GHz, and with bit-switch energy below 1 aJ. Small SFQ microprocessors have been developed, but characteristics inherent to SFQ circuits and the lack of circuit design tools have hampered the development of large SFQ systems. SFQ circuit characteristics include fan-out of one and the subsequent demand for pulse splitters, gate-level clocking, susceptibility to magnetic fields and sensitivity to intra-gate and inter-gate inductance. Superconducting interconnects propagate data pulses at the speed of light, but suffer from reflections at vias that attenuate transmitted pulses. The recently started IARPA SuperTools program aims to deliver SFQ Computer-Aided Design (CAD) tools that can enable the successful design of 64 bit RISC processors given the characteristics of SFQ circuits. A discussion on the technology of SFQ circuits and the most modern SFQ fabrication processes is presented, with a focus on the unique electronic design automation CAD requirements for the design, layout and verification of SFQ circuits.
To enable the use of passive transmission lines (PTLs) for the interconnection of single-flux-quantum (SFQ) circuits, we have implemented a driver and a receiver and have developed a method for designing SFQ circuits with passive interconnections. Basic components and properties of passive interconnections, such as the frequency characteristics of the driver and receiver, the PTL delay, and the crosstalk between PTLs, have been experimentally verified. Our developed components and design method have been applied to actual SFQ circuits, such as a 4 x 4 switch having block-to-block passive interconnections and a 2 x 2 switch having gate-to-gate passive interconnections. We have also shown the advantages of PTLs over Josephson transmission lines (JTLs). We also discuss the prospects of SFO circuits having passive interconnections.