Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Journal of Computational Electronics

An FPGA-based real quantum computer emulator

Jakub Pilch, Jacek Długopolski

Published Dec 15, 2018• 36 citations
Publisher

Abstract

While we cannot efficiently emulate quantum algorithms on classical architectures, we can move the weight of complexity from time to hardware resources. This paper describes a proposition of a universal and scalable quantum computer emulator, in which the FPGA hardware emulates the behavior of a real quantum system, capable of running quantum algorithms while maintaining their natural time complexity. The article also shows the proposed quantum emulator architecture, exposing a standard programming interface, and working results of an implementation of an exemplary quantum algorithm.

DOI
10.1007/s10825-018-1287-5

Related papers

Efficient emulation of quantum circuits on classical hardware

Calebe Micael de Oliveira Conceicao, Ricardo A. L. Reis

Current approaches for emulation of quantum algorithms on classical parallel hardware like FPGA suffer with three main issues: exponential usage of logic elements, synthesis takes exponential time and difficulty of implementation. In this paper we propose a processor architecture capable of efficiently emulate quantum circuits, reducing the mishaps of previous similar proposals. We compare our results to previous works with respect to a common benchmark and validate the architecture using FPGA. Our approach has better scalability in logic cell usage, a better management of the need of re-synthesis and easier implementation.

IEEE Latin American Symposium on Circuits and Systems (LASCAS)•Feb 1, 2015•9 citations

Towards Higher Scalability of Quantum Hardware Emulation Using Efficient Resource Scheduling

Naveed Mahmud, Esam El‐Araby

Quantum algorithms can be efficiently emulated on classical hardware such as field programmable gate arrays (FPGAs), achieving significant speedup over software simulations. However, the increase in the required hardware resources for emulating quantum systems becomes a critical limitation as the number of qubits is increased. In this paper, we propose a scalable emulation framework for modeling quantum algorithms on FPGAs that employs efficient resource scheduling such as space and space-time scheduling. In addition, full floating point precision arithmetic and dataflow non-linear (dynamic) pipelining are also used to achieve higher accuracy and higher throughput. We propose scalable and optimized hardware architectures for Quantum Fourier Transform (QFT) and Grover's search algorithm and demonstrate the scalability of our framework by scaling the system up to 5 fully-entangled qubits. A multi-node (multi-FPGA), state-of-the-art high-performance reconfigurable computer (HPRC) was used for implementation of the proposed architectures. Our experimental results show that by employing efficient resource scheduling techniques, the hardware resource constraints could be mitigated and the proposed emulation framework could be made feasible for emulation of more complex, larger-scale quantum algorithms while maintaining higher accuracy and throughput than existing work.

IEEE International Conference on Rebooting Computing (ICRC)•Nov 1, 2018•9 citations

An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture

Y. H. Lee, Mohamed Khalil-Hani, Muhammad Nadzir Marsono

Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA) is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits.

International Journal of Reconfigurable Computing•Jan 1, 2016•38 citations

A Scalable High-Precision and High-Throughput Architecture for Emulation of Quantum Algorithms

Naveed Mahmud, Esam El‐Araby

Quantum hardware emulators using field programmable gate arrays (FPGAs) have been demonstrated to efficiently exploit the inherent parallelism of quantum algorithms and perform better than sequential software simulators. However, one key problem in mapping quantum circuits on FPGAs is the exponential increase in resource requirements with the increase in the number of quantum bits (qubits). As a result, the precision of hardware emulators is often reduced to save resources and accommodate larger quantum circuits which results in lower accuracy and lower throughput. In this paper, we present a full precision FPGA quantum emulator that uses 32-bit floating-point arithmetic and has a fully pipelined architecture. Our emulator is capable of emulating an entangled 4-qubit quantum system performing Quantum Fourier Transform, Grover's Search algorithms on a single FPGA node. Our experimental work was conducted on a highly scalable multi-node (multi-FPGA) state-of-the-art high-performance reconfigurable computer (HPRC). Experimental results show that our emulator is functionally accurate and has a higher operating frequency relative to other emulators. For emulating larger-scale circuits we propose using a multi-node architecture scheme with low latency, high bandwidth inter-node communication.

IEEE International System-on-Chip Conference (SOCC)•Sep 1, 2018•12 citations

FPGA-based emulation framework for two-qubit quantum computation: Design, implementation, and validation

Arfeen Zahra, Madiha Khalid, Naveed Riaz +3 more

Quantum computing leverages quantum mechanics to perform complex computations efficiently, yet its practical implementation is hindered by hardware-software interdependence and quantum state instability. This paper advances lightweight FPGA-based quantum emulation by incorporating a universal quantum gate set, including parameterized Phase gates and the CNOT gate, to support comprehensive quantum protocol emulation on FPGA hardware. The FPGA platform used for synthesis is Artix-7. The proposed emulator is validated through simulations of quantum circuits, including Bell States, the Deutsch algorithm, Superdense coding, Grover's search, and BB84 QKD, with results benchmarked against IBM's noiseless quantum simulator. Utilizing FPGA's customizable parallelism and energy efficiency, this framework offers a resource-efficient, reliable platform for developing and testing quantum algorithms.

PLoS ONE•Aug 24, 2026•0 citations

Improving Emulation of Quantum Algorithms using Space-Efficient Hardware Architectures

Naveed Mahmud, Esam El‐Araby

With rapid advancement in quantum computing technology, continuous efforts are being directed to simulation and emulation of quantum algorithms on classical platforms. A well-known limitation to classical emulation of quantum circuits is scalability. Existing hardware emulators implement gate-based circuit models of quantum circuits that result in heavy resource utilization and degrade the scalability of the system. Also, current quantum emulation hardware use fixedpoint arithmetic, which has an adverse effect on accuracy when the system is scaled up. In this work, we employ a complexmultiply-and-accumulate (CMAC) and lookup-based emulation approach that greatly reduces resource utilization and improves system scalability in terms of number of emulated qubits. We demonstrate emulation of up to 16 fully-entangled qubits which is highest among existing work. We design fully-pipelined, highthroughput hardware architectures that use floating-point precision for higher accuracy. Experimental evaluation and analysis of the architectures in terms of speed and area is also provided. The emulator is prototyped on a high-performance reconfigurable computing (HPRC) system and our results demonstrate quantitative improvement over existing Field-Programmable-Gate-Array (FPGA)-based hardware emulators.

IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)•Jul 1, 2019•2 citations
While we cannot efficiently emulate quantum algorithms on classical architectures, we can move the weight of complexity from time to hardware resources. This paper describes a proposition of a universal and scalable quantum computer emulator, in which the FPGA hardware emulates the behavior of a real quantum system, capable of running quantum algorithms while maintaining their natural time complexity. The article also shows the proposed quantum emulator architecture, exposing a standard programming interface, and working results of an implementation of an exemplary quantum algorithm.
Current approaches for emulation of quantum algorithms on classical parallel hardware like FPGA suffer with three main issues: exponential usage of logic elements, synthesis takes exponential time and difficulty of implementation. In this paper we propose a processor architecture capable of efficiently emulate quantum circuits, reducing the mishaps of previous similar proposals. We compare our results to previous works with respect to a common benchmark and validate the architecture using FPGA. Our approach has better scalability in logic cell usage, a better management of the need of re-synthesis and easier implementation.
Quantum algorithms can be efficiently emulated on classical hardware such as field programmable gate arrays (FPGAs), achieving significant speedup over software simulations. However, the increase in the required hardware resources for emulating quantum systems becomes a critical limitation as the number of qubits is increased. In this paper, we propose a scalable emulation framework for modeling quantum algorithms on FPGAs that employs efficient resource scheduling such as space and space-time scheduling. In addition, full floating point precision arithmetic and dataflow non-linear (dynamic) pipelining are also used to achieve higher accuracy and higher throughput. We propose scalable and optimized hardware architectures for Quantum Fourier Transform (QFT) and Grover's search algorithm and demonstrate the scalability of our framework by scaling the system up to 5 fully-entangled qubits. A multi-node (multi-FPGA), state-of-the-art high-performance reconfigurable computer (HPRC) was used for implementation of the proposed architectures. Our experimental results show that by employing efficient resource scheduling techniques, the hardware resource constraints could be mitigated and the proposed emulation framework could be made feasible for emulation of more complex, larger-scale quantum algorithms while maintaining higher accuracy and throughput than existing work.
Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA) is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource utilization is attained against the pipeline implementations proposed in prior works. The proposed work contributes to the formulation of a proof-of-concept baseline FPGA emulation framework with optimization on datapath designs that can be extended to emulate practical large-scale quantum circuits.
Quantum hardware emulators using field programmable gate arrays (FPGAs) have been demonstrated to efficiently exploit the inherent parallelism of quantum algorithms and perform better than sequential software simulators. However, one key problem in mapping quantum circuits on FPGAs is the exponential increase in resource requirements with the increase in the number of quantum bits (qubits). As a result, the precision of hardware emulators is often reduced to save resources and accommodate larger quantum circuits which results in lower accuracy and lower throughput. In this paper, we present a full precision FPGA quantum emulator that uses 32-bit floating-point arithmetic and has a fully pipelined architecture. Our emulator is capable of emulating an entangled 4-qubit quantum system performing Quantum Fourier Transform, Grover's Search algorithms on a single FPGA node. Our experimental work was conducted on a highly scalable multi-node (multi-FPGA) state-of-the-art high-performance reconfigurable computer (HPRC). Experimental results show that our emulator is functionally accurate and has a higher operating frequency relative to other emulators. For emulating larger-scale circuits we propose using a multi-node architecture scheme with low latency, high bandwidth inter-node communication.
Quantum computing leverages quantum mechanics to perform complex computations efficiently, yet its practical implementation is hindered by hardware-software interdependence and quantum state instability. This paper advances lightweight FPGA-based quantum emulation by incorporating a universal quantum gate set, including parameterized Phase gates and the CNOT gate, to support comprehensive quantum protocol emulation on FPGA hardware. The FPGA platform used for synthesis is Artix-7. The proposed emulator is validated through simulations of quantum circuits, including Bell States, the Deutsch algorithm, Superdense coding, Grover's search, and BB84 QKD, with results benchmarked against IBM's noiseless quantum simulator. Utilizing FPGA's customizable parallelism and energy efficiency, this framework offers a resource-efficient, reliable platform for developing and testing quantum algorithms.
With rapid advancement in quantum computing technology, continuous efforts are being directed to simulation and emulation of quantum algorithms on classical platforms. A well-known limitation to classical emulation of quantum circuits is scalability. Existing hardware emulators implement gate-based circuit models of quantum circuits that result in heavy resource utilization and degrade the scalability of the system. Also, current quantum emulation hardware use fixedpoint arithmetic, which has an adverse effect on accuracy when the system is scaled up. In this work, we employ a complexmultiply-and-accumulate (CMAC) and lookup-based emulation approach that greatly reduces resource utilization and improves system scalability in terms of number of emulated qubits. We demonstrate emulation of up to 16 fully-entangled qubits which is highest among existing work. We design fully-pipelined, highthroughput hardware architectures that use floating-point precision for higher accuracy. Experimental evaluation and analysis of the architectures in terms of speed and area is also provided. The emulator is prototyped on a high-performance reconfigurable computing (HPRC) system and our results demonstrate quantitative improvement over existing Field-Programmable-Gate-Array (FPGA)-based hardware emulators.