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Proceedings of the IEICE General Conference

C-8-2 Operation of RSFQ library cells fabricated by using a 10-kA/cm^2 Nb junction technology

Masaaki Maezawa, Masayuki OCHIAI, Hiroe Kimura, Fuminori Hirayama, Motohiro Suzuki

Published Mar 8, 2006• 0 citations
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Design and Operation of RSFQ Cell Library Fabricated by Using a 10-kA/cm2{\rm kA/cm}^{2}kA/cm2 Nb Technology
A 10-kA/cm2Nb/AlOchi/Nb junction technology for rapid single flux quantum (RSFQ) integrated circuits has been developed. Modifying our standard 1.6-kA/cm2cell library, we have implemented elementary cells used to build RSFQ digital-to-analog converters for ac voltage standard applications. The 10-kA/cm2library cells have been fabricated by utilizing existing process tools. Correct operations of the circuits have been confirmed at low speed. The maximum operating frequencies evaluated by an average-voltage measurement technique were consistent with the scaling rules of RSFQ circuits.
We have proposed a cell-based design approach for rapid single flux quantum (RSFQ) logic circuits. In our design approach, a binary decision diagram (BDD) is used for representation of logical functions in order to reduce the number of gates. We have made a standard cell library, which is composed of only five basic cells. We add one-junction Josephson transmission line (JTL) to the edge of the input and the output node of some basic cells, by which no deterioration of the DC bias margin is observed for the connection of each cell. In the layout level, the size and the position of the input/output node of each cell are equalized. The standard cell circuits were fabricated by NEC 2.5 kA/cm/sup 2/ and Hypres 1.0 kA/cm/sup 2/ Nb standard process and they were tested at low speed.
Abstract Superconductor logic families can operate with small power dissipation and are thus suitable as building blocks for various computing systems. In some applications, superconductor logic circuits should be designed using Josephson junctions with low I c values ( I c : critical current). For instance, lowering I c values enables qubit interface circuits to operate with very small power dissipation at ~10 mK and stochastic electronics to easily induce stochastic operations. In this study, we develop the AIST 1 kA cm −2 Nb planarized process (1KP) with a minimum critical current of 10 µA, dedicated to the design of qubit interface circuits and stochastic electronics. We also develop rapid single-flux-quantum (RSFQ) and adiabatic quantum-flux-parametron (AQFP) cell libraries using the 1KP. The power dissipation of RSFQ logic using the 1KP can be reduced to 3.2% of that for conventional RSFQ logic by reducing both I c values and a bias voltage. Furthermore, the amount of supply currents for AQFP circuits using the 1KP can be reduced to ~40% of that for conventional AQFP circuits due to a large mutual inductance between AQFP gates and excitation lines, which results from a reduction in I c and an increase in inductances. We demonstrate RSFQ and AQFP circuits fabricated by the 1KP at 4.2 K. These results indicate that RSFQ and AQFP circuits using the 1KP have the potential to be used for the design of qubit interface circuits and stochastic electronics.