Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Proceedings of the IEICE General Conference

C-8-3 Design of an SFQ Voltage Multiplier Utilizing a Higher-Order Step

Yoko Namatame, Kazuyuki Kato, Masataka Moriya, Koichi Usami, Tadayuki Kobayashi, Yoshinao Mizugaki, Masaaki Maezawa

Published Mar 8, 2006• 0 citations
OpenAlex

Related papers

A Compact Voltage Pulse Multiplier for SFQ Circuit Readout

Sasan Razmkhah, Ali Bozbey, Pascal Febvre

•Sep 1, 2019•0 citations

Operation of 1000-fold voltage multiplier using SFQ reflection at under-damped junctions

Yusuke Sato, Moriya Masataka, Shimada Hiroshi +2 more

IEICE Technical Report; IEICE Tech. Rep.•Jan 17, 2013•0 citations

Design and operation of 6-bit variable SFQ pulse number multiplier

Yoshitaka Takahashi, Moriya Masataka, Shimada Hiroshi +2 more

IEICE Technical Report; IEICE Tech. Rep.•Oct 18, 2012•0 citations

C-8-14 Design and Operation of 6-bit Variable SFQ Pulse Number Multiplier

Yoshinao Mizugaki, Jun Saito, Masataka Moriya +1 more

Proceedings of the Society Conference of IEICE•Aug 30, 2011•0 citations

Operation of Variable SFQ Pulse Number Multiplier Designed for D/A Converter

Jun Saito, Takeyuki Tanaka, Masataka Moriya +3 more

IEICE Technical Report; IEICE Tech. Rep.•Jan 13, 2010•0 citations

Design and functional tests of variable SFQ pulse number multiplier

J. Saito, T. Tanaka, Masataka Moriya +3 more

Physica C Superconductivity•May 21, 2011•6 citations