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International Symposium on Devices, Circuits and Systems (ISDCS)

Implementation of neareast neighbor quantum circuit with low quantum cost

Laxmidhar Biswal, Anirban Bhattachaijee, Sudip Ghosh, Hafizur Rahaman

Published Mar 1, 2018• 0 citations
Publisher

Abstract

Primary purpose behind this work is to develop a type of quantum gate C2(iZ)/C2(-iZ) derived from unitary quantum gate C2(-I) by finding its 2ndroot. This newly introduced gate is nearest-neighbor compliant with a unit quantum cost. The main objective in deriving this quantum gate C2(iZ)/C2(-iZ) is to generate low cost MCT gates which eventually produces cost optimized NNC free reversible circuits. For systematic mapping and a fair comparison with prior works, we formed a quantum gate library that includes CNOT, NOT, H, CH, C2(-I) and C2(iZ)/C2(-iZ) gates. A mapping algorithm including the complete gate library is proposed alongwith necessary mathematical proofs. Using the gate library, we show significant cost savings is achievable over the state-of-the-art approaches, when mapping n-control Toffoli gates and chosen benchmark functions.

DOI
10.1109/isdcs.2018.8379674

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Primary purpose behind this work is to develop a type of quantum gate C2(iZ)/C2(-iZ) derived from unitary quantum gate C2(-I) by finding its 2ndroot. This newly introduced gate is nearest-neighbor compliant with a unit quantum cost. The main objective in deriving this quantum gate C2(iZ)/C2(-iZ) is to generate low cost MCT gates which eventually produces cost optimized NNC free reversible circuits. For systematic mapping and a fair comparison with prior works, we formed a quantum gate library that includes CNOT, NOT, H, CH, C2(-I) and C2(iZ)/C2(-iZ) gates. A mapping algorithm including the complete gate library is proposed alongwith necessary mathematical proofs. Using the gate library, we show significant cost savings is achievable over the state-of-the-art approaches, when mapping n-control Toffoli gates and chosen benchmark functions.
Linear Nearest Neighbor (LNN) synthesis in reversible circuits has emerged as an important issue in terms of technological implementation for quantum computation. The objective is to obtain a LNN architecture with minimum gate cost. As achieving optimal synthesis is a hard problem, heuristic methods have been proposed in recent literature. In this work we present a graph partitioning based approach for LNN synthesis with reduction in circuit cost. In particular, the number of SWAP gates required to convert a given gate-level quantum circuit to its equivalent LNN configuration is minimized. Our algorithm determines the reordering of indices of the qubit line(s) for both single control and multiple controlled gates. Experimental results for placing the target qubits of Multiple Controlled Toffoli (MCT) library of benchmark circuits show a significant reduction in gate count and quantum gate cost compared to those of related research works.
Motivated by the prospects of quantum computation, the design of quantum circuits received significant attention in the recent past. Due to the complex representation of the underlying quantum mechanical phenomena, a two-stage design flow was established in which the desired functionality is first realized in terms of a reversible circuit and, afterwards, mapped into an equivalent quantum circuit. This paper proposes a new metric for estimating nearest neighbor cost at the reversible circuit level. Research works are mostly carried out considering nearest neighbor constraints at the quantum circuit level. Various quantum gate libraries and mapping schemes have been reported in the literature to realize the circuit operation at quantum level. One such mapping scheme exploiting a well established quantum gate library (NCV) is explored in defining the cost metric. Experimental evaluations confirmed both the accuracy as well as the applicability of the proposed metric.
The quest of achieving higher computing performance is driving the research on quantum computing, which is reporting new milestones almost on a daily basis. For practical quantum circuit design, fault tolerance is an essential condition. This is achieved by mapping the target functions into the Clifford+T group of elementary quantum gates. Furthermore, the application of error-correcting codes in quantum circuits requires the quantum gates to be formed between adjacent Qubits. In this work, we improve the state-of-the-art quantum circuit design by addressing both of the above challenges. First, we propose a novel mapping of Multiple-Control Toffoli (MCT) gates to Clifford+T group gates, which achieves lower gate count compared to earlier work. Secondly, we show a generic way to convert any Clifford+T circuit into a nearest neighbor one. We validate the efficacy of our approach with detailed experimental studies.
Multiple Control Toffoli (MCT) gates are the main constituent of reversible circuits. For quantum circuits, MCT gates are realized using quantum gate libraries such as NCV or NCVW which are composed of universal quantum gates like NOT, CNOT, V/V+, and W/W+. In order to improve the design of quantum circuits, the mapping of MCT gates to a cascade of these quantum gates has to be improved as well. In this work, we propose reconfigured structures of quantum gates realizing MCT gates. To this end, we rely on the established mapping structure, but append redundant gates which can be used afterwards for simplifications. Eventually, the proposed design is mapped to an NCVW quantum circuit. We have successfully tested our mapping technique. The obtained results have experimentally been compared to related work.
With the advancement of technological footprints, high-end computation techniques, like quantum computation, have made significant progress in the design industry. Although quantum computation has proved itself as the next-generation computing paradigm, it is facing several design challenges, and one such design issue is in the form of the Nearest Neighbour (NN)t. This much-talked NN property demands the qubits in operating quantum gates to be adjacent, and a circuit should satisfy this NN property to be eligible for implementation. Considering the importance of NN enforcement in implementing circuits, we introduce a synthesis approach for the efficient transformation of reversible circuits to equivalent LNN representations. Our main focus in this work is to minimize the use of SWAP gates in designing NN-satisfied MCT-based reversible circuits. Towards transforming input circuits to LNN architecture, we have exploited a template matching scheme followed by two-qubit reordering policies, global and local, to improve the NN designs and reduce SWAP utilization. In finding the global solution, here we have used a dynamic programming algorithm where the initial order of qubit lines gets changed, while a heuristic-based SWAP placement function is used for finding a local qubit order sequence. The proposed synthesis workflow has been tested over an extensive set of benchmark functions, and comparison with the reported design approaches showed a substantial reduction in cost parameters.