Motivated by the prospects of quantum computation, the design of quantum circuits received significant attention in the recent past. Due to the complex representation of the underlying quantum mechanical phenomena, a two-stage design flow was established in which the desired functionality is first realized in terms of a reversible circuit and, afterwards, mapped into an equivalent quantum circuit. This paper proposes a new metric for estimating nearest neighbor cost at the reversible circuit level. Research works are mostly carried out considering nearest neighbor constraints at the quantum circuit level. Various quantum gate libraries and mapping schemes have been reported in the literature to realize the circuit operation at quantum level. One such mapping scheme exploiting a well established quantum gate library (NCV) is explored in defining the cost metric. Experimental evaluations confirmed both the accuracy as well as the applicability of the proposed metric.
Motivated by the prospects of quantum computation, the design of quantum circuits received significant attention in the recent past. Due to the complex representation of the underlying quantum mechanical phenomena, a two-stage design flow was established in which the desired functionality is first realized in terms of a reversible circuit and, afterwards, mapped into an equivalent quantum circuit. This paper proposes a new metric for estimating nearest neighbor cost at the reversible circuit level. Research works are mostly carried out considering nearest neighbor constraints at the quantum circuit level. Various quantum gate libraries and mapping schemes have been reported in the literature to realize the circuit operation at quantum level. One such mapping scheme exploiting a well established quantum gate library (NCV) is explored in defining the cost metric. Experimental evaluations confirmed both the accuracy as well as the applicability of the proposed metric.
In recent years, quantum computing has gained a lot of importance due to its property of increasing computational power exponentially. In the current literature, it has observed that the quantum computing has potential to solve many complex problems with less complexity based on the theoretical analysis. But in contrast to hardware implementation of quantum technology, it expands in a linear way. Moreover, there is a close relation between quantum computing and reversible computing. More precisely, quantum computing operations are reversible. In this paper, we propose an extended approach of mapping flow for describing reversible circuits to its equivalent quantum circuits. Here, we consider the reversible circuits of n-inputs and n-outputs with NCT and GT library, which is mapped to the quantum circuits with the NCV-|v1〉 library. Finally, we provide our experimental results in terms of quantum costs for mapping the reversible circuits to quantum circuits.
With recent interest in reversible and quantum computation, research in synthesis of reversible and quantum circuits has increased in momentum. With additional requirements of neighborhood interactions among qubits (with two basis states) being a necessity in some physical realizations, several works on obtaining nearest neighbor quantum gate realization by inserting SWAP gates have been reported. These methods are based on two broad optimization approaches, one based on global ordering, where qubits are ordered over the whole netlist, and the other based on local ordering for minimizing SWAP gate insertions on smaller segments of netlists. Further reductions in cost are possible by using multi-valued qudits that have more than two basis states. The present paper considers a quantum circuit based on the NCV library, and proposes a better SWAP gate insertion method based on local ordering that uses an N-gate lookahead approach to reduce cost. Experimental results on benchmark circuits and comparison against published works confirm the benefits of the proposed approach, with improvements over reported works obtained in the range of 27%-43% on the average and 54%-63% in the best case. The method is also scalable for larger circuits, with the longest runtime observed as 10 minutes.
Many synthesis approaches for reversible and quantum logic have been proposed so far. However, most of them generate circuits with respect to simple metrics, i.e. gate count or quantum cost. On the other hand, to physically realize reversible and quantum hardware, additional constraints exist. In this paper, we describe cost metrics beyond gate count and quantum cost that should be considered while synthesizing reversible and quantum logic for the respective target technologies. We show that the evaluation of a synthesis approach may differ if additional costs are applied. In addition, a new cost metric, namely Nearest Neighbor Cost (NNC) which is imposed by realistic physical quantum architectures, is considered in detail. We discuss how existing synthesis flows can be extended to generate optimal circuits with respect to NNC while still keeping the quantum cost small.
Linear Nearest Neighbor (LNN) synthesis in reversible circuits has emerged as an important issue in terms of technological implementation for quantum computation. The objective is to obtain a LNN architecture with minimum gate cost. As achieving optimal synthesis is a hard problem, heuristic methods have been proposed in recent literature. In this work we present a graph partitioning based approach for LNN synthesis with reduction in circuit cost. In particular, the number of SWAP gates required to convert a given gate-level quantum circuit to its equivalent LNN configuration is minimized. Our algorithm determines the reordering of indices of the qubit line(s) for both single control and multiple controlled gates. Experimental results for placing the target qubits of Multiple Controlled Toffoli (MCT) library of benchmark circuits show a significant reduction in gate count and quantum gate cost compared to those of related research works.
Since decades, quantum computing has received tremendous attention among the researchers due to its dominance over classical computing. But simultaneously it has faced some design challenges and implementation constraints in this long run. One such constraint to build quantum circuits is to satisfy the so-called Nearest Neighbor (NN) property in the implemented circuits. Using SWAP gates, this constraint can be satisfied. But this leads to another design issue, namely how to determine such NN designs with a minimum use of SWAP gates. In way to further explore this area, in this work, we propose a heuristic approach for efficient NN complaint representation of quantum circuits in 2D space. The developed technique is segmented in three stages - qubit selection, qubit placement and SWAP gate insertion. The stated approach has been tested over a wide spectrum of benchmarks and reductions in cost parameters are observed. Improvement of more than 17%, 3% over 2D designs and 35%, 22% over 1D designs on SWAP count and quantum cost can be reported, respectively.
Quantum information processing is of interest as it offers the potential for a new generation of very powerful computers supporting novel computational paradigms. Over the last couple of decades, different aspects of quantum computers ranging from quantum algorithms to quantum physical design have received growing attention. One of the most important research areas is the synthesis and post-synthesis optimization of reversible and quantum circuits. Many synthesis and optimization approaches can be found in the literature, yet, due to the complexity of the problem, finding approaches leading to optimal, or near optimal, results is still an open problem. The synthesized circuits are usually evaluated based on quantum cost models. Therefore, they are often technology mapped to circuits of more primitive gates. To this end, various technology mapping approaches have also been proposed in the past few years. Related work shows an existing gap in optimized technology mapping for reversible and quantum circuits. In this dissertation, an optimized technology mapping design flow is introduced for mapping reversible circuits to quantum circuits. The contributions of this dissertation are classified as follows: - New reversible circuit optimization methods. - Optimized reversible to quantum mapping approaches. - New quantum gate libraries and new cost models for reversible gates based on the new libraries. - Quantum circuit optimization approaches. The steps above, form an optimized flow for mapping reversible circuits to quantum circuits. At each step of the design flow optimized and consistent approaches are suggested with the goal of reducing the quantum cost of the synthesized reversible circuits. The evaluations show that the proposed mapping methodology leads to significant improvement in the quantum cost of the existing benchmark circuits.