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IEEE Information Theory Workshop (ITW)

Lowering the error floors of low-density parity-check codes with additional check nodes

Dongming Yuan, Lu Li, Yuanan Liu

Published Nov 1, 2017• 5 citations
Publisher

Abstract

This paper proposes a novel scheme for bit recovery of Low-Density Parity-Check (LDPC) Codes. Firstly, the most erroneous and the most reliable bits are located by searching the codeword bits. Subsequently, new check nodes are added to connect them, thus the negative effects of the most erroneous bits along with the corresponding trapping sets are avoided. Eventually, the BER performance is dramatically improved in the error-floor region according to the simulated results. This idea could be a more concise and simple alternative to weaken the effects of trapping sets in LDPC applications.

DOI
10.1109/itw.2017.8277936

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This paper proposes a novel scheme for bit recovery of Low-Density Parity-Check (LDPC) Codes. Firstly, the most erroneous and the most reliable bits are located by searching the codeword bits. Subsequently, new check nodes are added to connect them, thus the negative effects of the most erroneous bits along with the corresponding trapping sets are avoided. Eventually, the BER performance is dramatically improved in the error-floor region according to the simulated results. This idea could be a more concise and simple alternative to weaken the effects of trapping sets in LDPC applications.
In this paper, a modified sum-product algorithm to correct bit errors captured within the trapping sets, which are produced in decoding of low-density parity-check (LDPC) codes, is proposed. Unlike the original sum-product algorithm, the proposed decoding method consists of two stages. Whether the main cause of decoding failure is the trapping sets or not is determined at the first stage. And the bit errors within the trapping sets are corrected at the second stage. In the modified algorithm, the set of failed check nodes and the transition patterns of hard-decision bits are exploited to search variable nodes in the trapping sets. After inverting information of the variable nodes, the sum-product algorithm is carried out to correct the bit errors. As a result of simulation, the proposed algorithm shows continuously improved error performance with increase in the signal-to-noise ratio. It is, therefore, considered that the modified sum-product algorithm significantly reduces or possibly eliminates the error floor in LDPC codes.
Trapping sets strongly degrade performance of low-density parity check (LDPC) codes in the low-error-rate region. This creates significant difficulties for the deployment of LDPC codes to low-error-rate applications such as storage and wireless systems with no or limited retransmission options. We propose a novel technique for breaking trapping sets based on collaborative decoding that utilizes two different decoding modes. While the main decoding mode executes message passing based on the original parity check matrix of the corresponding LDPC code, the sub-decoding mode operates on a modified parity check matrix formed by removing a portion of check nodes in the factor graph representation of the given code. The modified parity check matrix is designed to promote a passing of correct information into erroneous variable nodes in the trapping set. Theoretical properties of the proposed trapping-set-breaking technique have been established based on the notion of the improved separation for the trapped variable nodes. Simulation results show that the proposed collaborative LDPC decoding scheme switching between the two decoding modes back and forth effectively breaks dominant trapping sets of various known types of regular and irregular LDPC codes.
Low-Density Parity-Check (LDPC) codes have extensive applications in numerous communication systems. However, iterative LDPC decoders may suffer from error floor. In this paper, a low complexity post processing scheme (PPS) is proposed to significantly improve the error correction performance of a Min-Sum based LDPC decoder in the error floor region. Instead of using trapping set elimination algorithms, the proposed PPS introduces perturbations so that a decoder can escape from undesired local maximums. After decoding failure, for these unreliable code bits, the proposed PPS generates carefully modified soft messages, which are employed in the following decoding iterations. Numerical results demonstrate that the presented PPS significantly lowers the error floor for simulated LDPC codes.
Trapping sets have been identified as one of the main factors causing error floors of low-density parity-check (LDPC) codes at high SNR values. By adding several new rows to the original parity-check matrix, a novel method is proposed to eliminate small trapping sets in the LDPC code's Tanner graph. Based on this parity-check matrix extension, we design new codes with low error floors from the original irregular LDPC codes. Simulation results show that the proposed method can lower the error floors of irregular LDPC codes significantly at high SNR values over AWGN channels.