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National Conference on Communications

Additional check node to improve the performance of LDPC codes in the error floor region

Kuntal Deka, A. Rajesh, Prabin Kumar Bora

Published Feb 1, 2012• 0 citations
Publisher

Abstract

This paper presents a new scheme to reduce the detrimental effect of the trapping sets in the regular and irregular low density parity check (LDPC) codes. By adding only one new check node and properly selecting its edges, the performance in the error floor region can be improved. Simulation results show that the proposed scheme decreases the bit error rate (BER) and frame error rate (FER) significantly in the high signal-to-noise ratio (SNR) region at the expense of negligible rate loss.

DOI
10.1109/ncc.2012.6176774

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This paper presents a new scheme to reduce the detrimental effect of the trapping sets in the regular and irregular low density parity check (LDPC) codes. By adding only one new check node and properly selecting its edges, the performance in the error floor region can be improved. Simulation results show that the proposed scheme decreases the bit error rate (BER) and frame error rate (FER) significantly in the high signal-to-noise ratio (SNR) region at the expense of negligible rate loss.
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Elementary trapping sets (ETSs) have been found to be the main cause of error floor in the decoding of low-density parity-check (LDPC) codes. Moreover, irregular LDPC codes that avoid harmful [w; u; e] ETSs have been constructed and have shown to possess superior error performance compared with other LDPC codes. In this paper, we attempt to evaluate irregular LDPC code performance under an additive white Gaussian noise channel within the high SNR region using the importance sampling (IS) approach in conjunction with the identification of [w; u; e] ETSs. For any given irregular LDPC code, we will first apply a three-step method that aims to search as many ETSs within the code as possible. Then, we will classify these ETSs into different groups based on their labels, i.e., [w; u; e]'s. Further, by dividing the error region into various sub-regions centered by ETSs, we apply the IS simulator to evaluate the error rate of each of the sub-regions. Based on the error rates of all the sub-regions, we can estimate the overall error rate of the LDPC code. Results have indicated that our proposed IS scheme can produce speed-up gains up to 3.9×109 times compared to Monte Carlo simulations.
Trapping sets have been identified as one of the main factors causing error floors of low-density parity-check (LDPC) codes at high SNR values. By adding several new rows to the original parity-check matrix, a novel method is proposed to eliminate small trapping sets in the LDPC code's Tanner graph. Based on this parity-check matrix extension, we design new codes with low error floors from the original irregular LDPC codes. Simulation results show that the proposed method can lower the error floors of irregular LDPC codes significantly at high SNR values over AWGN channels.
The progressive-edge-growth (PEG) algorithm of Hu et al. is modified to improve the error floor performance of the constructed low-density parity-check (LDPC) codes. To improve the error floor, the original PEG algorithm is equipped with an efficient algorithm to find the dominant elementary trapping sets (ETS's) that are added to the Tanner graph of the under-construction code by the addition of each variable node and its adjacent edges. The aim is to select the edges, among the candidates available at each step of the original PEG algorithm, that prevent the creation of dominant ETS's. The proposed method is applicable to both regular and irregular variable node degree distributions. Simulation results are presented to demonstrate the superior ETS distribution and error floor performance of the constructed codes compared to similar codes constructed by the original and other modifications of the PEG algorithm.
We discuss error floor asympotics and present a method for improving the performance of low-density parity check (LDPC) codes in the high SNR (error floor) region. The method is based on Tanner graph covers that do not have trapping sets from the original code. The advantages of the method are that it is universal, as it can be applied to any LDPC code/channel/decoding algorithm and it improves performance at the expense of increasing the code length, without losing the code regularity, without changing the decoding algorithm, and, under certain conditions, without lowering the code rate. The proposed method can be modified to construct convolutional LDPC codes also. The method is illustrated by modifying Tanner, MacKay and Margulis codes to improve performance on the binary symmetric channel (BSC) under the Gallager B decoding algorithm. Decoding results on AWGN channel are also presented to illustrate that optimizing codes for one channel/decoding algorithm can lead to performance improvement on other channels.