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Bulletin of the American Physical Society

Die Design and Fabrication for Flip-Chip-Packaged Superconducting Quantum Processors

Román Caudillo, Zachary Yoscovits, Lester F. Lampert, David J. Michalak, Adel A. Elsherbini, Javier Falcon, Jeanette M. Roberts, L. DiCarlo, James S. Clarke

Published Mar 8, 2018• 1 citation
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This paper discusses the major challenges and solutions in designing high-performance superconductor processors in the context of the on-going collaboration between SUNY Stony Brook, TRW, and the JPL (NASA). It presents the architecture and organization of the first 8-bit FLUX-1 RSFQ microprocessor with a target clock frequency of 20 GHz fabricated in TRW's 4 kA/cm/sup 2/, 1.75-/spl mu/m Josephson junction technology in 2001-2002. A new parallel partitioned architecture has been developed for FLUX-1 in order to fill its long processing pipelines with operations, and reduce interconnect delays. The latest version of FLUX-1, called FLUX-1R, with improved circuit design characteristics and decreased power dissipation was fabricated in July 2002. FLUX-1R contains 63,107 Josephson junctions on a 10.35 mm /spl times/10.65 mm die with flip-chip packaging. The chip is currently under testing at TRW.
The first single-chip superconductor FLUX-1 microprocessor has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using 4 kA/cm2, 1.75-μm Nb/AlOx/Nb Josephson junction technology as a result of the collaboration between SUNY Stony Brook and TRW, Inc. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor prototype with a target clock frequency of 17-20 GHz. A new parallel partitioned architecture has been developed in order to tolerate interconnect delays and fill long FLUX-1 processor pipelines with useful instructions. The processor includes the 16 × 32-bit pipelined instruction memory, 8 integer arithmetic-logic units interleaved with 8 registers, the branch unit, and I/O ports for 5-GHz chip-to-chip communication over Nb microstrip lines on a chip carrier. The FLUX-1 instruction set consists of ~25 arithmetic, logical, and control instructions. A FLUX-1 microprocessor chip contains 65,759 Josephson junctions on a 10.6 mm × 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in August 2001 are currently under testing at TRW, Inc.
This paper presents the design, simulation, and fabrication process of a superconducting single qubit utilizing Josephson junctions in both planar and flip-chip architectures. The Xmon qubit, characterized by its cross-shaped coplanar waveguide structure and high scalability, is employed to demonstrate the enhancement in coherence, connectivity, and control speed. The Xmon qubit was modeled and validated using Python, Ansys HFSS, and Sonnet software. The fabrication process, including the transmission line and Josephson junction, is also introduced.