Short-length scale-free low-density-paritycheck (SF-LDPC) codes have been found to outperform codes optimized by the density-evolution technique. However, a large fraction of degree-2 variable nodes will exist in SF-LDPC codes when the code rate is high. Consequently, small-size cycles with no external connections can easily be created by these degree-2 nodes, producing a large error rate. In this paper, we propose constraining the proportion of degree-2 variable nodes in the design SF-LDPC codes. We will evaluate the error performance of the high-rate SFLDPC codes under the new constraint.
Short-length scale-free low-density-paritycheck (SF-LDPC) codes have been found to outperform codes optimized by the density-evolution technique. However, a large fraction of degree-2 variable nodes will exist in SF-LDPC codes when the code rate is high. Consequently, small-size cycles with no external connections can easily be created by these degree-2 nodes, producing a large error rate. In this paper, we propose constraining the proportion of degree-2 variable nodes in the design SF-LDPC codes. We will evaluate the error performance of the high-rate SFLDPC codes under the new constraint.
Low-density parity-check (LDPC) codes with scale-free (SF) symbol-node degree distribution have been shown to provide very good error performance. When the code rate becomes high, however, there will be a lot of degree-2 symbol nodes in the “pure” SF-LDPC codes. As a consequence, when the codes are constructed by connecting the symbol nodes with the check nodes, many small-size cycles will be formed. Such small-cycles will degrade the error performance of the codes. In this paper, we address the issue by imposing a new constraint on the design of high-rate SF-LDPC codes. We will compare the error rates of the constrained SF-LDPC codes and other optimized LDPC codes.
Low-density parity-check (LDPC) codes can approach the Shannon limit performance closely, and are becoming one of the most promising channel codes in the Error Control Coding area.The performance of an LDPC code with given length is mainly affected by the sizes of some combinatorial characteristics of its corresponding bipartite graph and the distribution of variable degrees and check node degrees.With the help of the density evolution algorithm, randomly designed LDPC codes, with carefully chosen degree distribution pairs, have been shown to achieve better Shannon capacity performance than their regular counterparts when decoded using the iterative belief propagation (BP) decoding algorithm.However, regular LDPC codes outperform their irregular counterparts in term of their error floors.Therefore, construction of LDPC codes which have both attractive error rate performance and low error floor performance has become an attractive topic.Currently, optimization of variable node degree distribution and check node degree distribution for an LDPC code with given length, which could help the code to achieve good Shannon limit performance, has been extensively studied.In this dissertation, we demonstrate some approaches of improving the error floor performance for a given LDPC code with desired degree distribution pair.The contribution mainly includes three parts.In the first part, the relationship between cycles and unfavorable combinatorial
It is a challenge to design high-rate LDPC codes,especially with short length. Two-edge type LDPC( TET-LDPC) codes proposed recently have been shown to possess better performance than conventional LDPC codes at high rate. In this paper,structural advantages of TET-LDPC codes are investigated. Based on the advantages,a novel approach to design TET-LDPC codes at high rate is proposed,which aims to improve the performance by choosing a suitable degree for punctured variable nodes and optimizing the connections between variable nodes and check nodes. The simulation results show that the short-length high-rate TET-LDPC codes designed by the proposed approach can not only outperform conventional LDPC codes and conventional TET-LDPC codes,but also have lower error floors.
Finding coding schemes that approach the Shannon capacity limit has been the central theme during the development of error-control coding (ECC).In recent years low-density parity-check (LDPC) codes, due to their remarkable performance under iterative decoding, have received extensive study and have been adopted by many modern advanced communication systems.LDPC codes can be further extended to generalized LDPC (GLDPC) codes and doublygeneralized LDPC (DGLDPC) codes.GLDPC and DGLDPC codes are supersets of LDPC codes that possess more generic code structures.GLDPC and DGLDPC codes are more flexible than LDPC codes, since a richer variety of check nodes (CNs) or variable nodes (VNs) offers additional options and flexibility, which enable many advantages over LDPC codes in numerous scenarios.In this dissertation we focus on improved design methods for finite-length (FL) GLDPC and DGLDPC codes.The first research topic is the error floor behavior of FL-GLDPC and FL-DGLDPC codes.In GLDPC and DGLDPC codes, the existence of generalized CNs and VNs requires more careful management of edge connections for achieving low error floors.In this work the approximate cycle extrinsic message degree (ACE), a cycle parameter used in LDPC codes that reflects the resilience of the cycle to the noise, is generalized to extended ACE (eACE) for GLDPC and DGLDPC codes.By integrating eACE into the progressive-edge-growth (PEG) algorithm and adding more constraints on the connectivity of nodes, the error floor performance of GLDPC and DGLDPC codes can be greatly improved.In practice, designing codes capable of fast encoding is an important issue.Efficiently-encodable (EE) GLDPC and DGLDPC codes are studied and a self-consistent unified framework is proposed for constructing EE iteratively-decodable block codes, including EE-LDPC, EE-GLDPC and EE-DGLDPC codes.The competing nature of the fast encoding speed and the low error floor performance iv Abstract v is analyzed and verified via various simulation results.EE codes are systematic and suitable for puncturing; therefore, they are good candidates for rate-compatible (RC) data transmissions.Based on the characteristics of GLDPC and DGLDPC codes, we devise several systematic puncturing algorithms to provide good puncturing patterns for them.It is shown that we can significantly improve the code performance compared with random puncturing.Over a wide range of code rates, RC EE-GLDPC and EE-DGLDPC codes show advantages over EE-LDPC codes, especially at high signal-to-noise ratios (SNRs).
Existing design methods for irregular Low-Density Parity-Check (LDPC) codes over the additive white Gaussian noise channel are based on using asymptotic analysis tools such as density evolution in an optimization process. Such a process is computationally expensive particularly when a large number of constituent variable node degrees are involved in the design. In this paper, we propose a systematic approach for the design of irregular LDPC codes. The proposed method, which is based on a pre-computed upper bound on the fraction of edges connected to variable nodes of degree 3, is considerably less complex than the conventional optimization approach. Through a number of examples, we demonstrate that using our method, ensembles with performance very close to those devised based on optimization, can be designed. In addition to having very good performance, the number of constituent variable node degrees in the designed ensembles is only three or four. This, in some cases, is much smaller than the corresponding number for optimization-based designs with similar performance.
Low-density parity-check (LDPC) codes have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost, time, power and bandwidth requirements of target applications. The constructed codes should also meet error rate performance requirements of those applications. Since their rediscovery, there has been much research work on LDPC code construction and implementation. LDPC codes can be designed over a wide space with parameters such as girth, rate and length. There is no unique method of constructing LDPC codes. Existing construction methods are limited in some way in producing good error correcting performing and easily implementable codes for a given rate and length. There is a need to develop methods of constructing codes over a wide range of rates and lengths with good performance and ease of hardware implementability. LDPC code hardware design and implementation depend on the structure of target LDPC code and is also as varied as LDPC matrix designs and constructions. There are several factors to be considered including decoding algorithm computations,processing nodes interconnection network, number of processing nodes, amount of memory, number of quantization bits and decoding delay. All of these issues can be handled in several different ways. \nThis thesis is about construction of LDPC codes and their hardware implementation. LDPC code construction and implementation issues mentioned above are too many to be addressed in one thesis. The main contribution of this thesis is the development of LDPC code construction methods for some classes of structured LDPC codes and techniques for reducing decoding time. We introduce two main methods for constructing structured codes. In the first method, column-weight two LDPC codes are derived from distance graphs. A wide range of girths, rates and lengths are obtained compared to existing methods. The performance and implementation complexity of obtained codes depends on the structure of their corresponding distance graphs. In the second method, a search algorithm based on bit-filing and progressive-edge growth algorithms is introduced for constructing quasi-cyclic LDPC codes. The algorithm can be used to form a distance or Tanner graph of a code. This method could also obtain codes over a wide range of parameters. Cycles of length four are avoided by observing the row-column constraint. \nRow-column connections observing this condition are searched sequentially or randomly. Although the girth conditions are not sufficient beyond six, larger girths codes were easily obtained especially at low rates. The advantage of this algorithm compared to other methods is its flexibility. It could be used to construct codes for a given rate and length with girths of at least six for any sub-matrix configuration or rearrangement. The code size is also easily varied by increasing or decreasing sub-matrix size. Codes obtained using a sequential search criteria show poor performance at low girths (6 and 8) while random searches result in good performing codes. \nQuasi-cyclic codes could be implemented in a variety of decoder architectures. One of the many options is the choice of processing nodes interconnect. We show how quasi-cyclic codes processing could be scheduled through a multistage network. Although these net-works have more delay than other modes of communication, they offer more flexibility at a reasonable cost. Banyan and Benes networks are suggested as the most suitable networks. \nDecoding delay is also one of several issues considered in decoder design and implementation. In this thesis, we overlap check and variable node computations to reduce decoding time. Three techniques are discussed, two of which are introduced in this thesis. The techniques are code matrix permutation, matrix space restriction and sub-matrix row-column scheduling. Matrix permutation rearranges the parity-check matrix such that rows and columns that do not have connections in common are separated. This techniques can be applied to any matrix. Its effectiveness largely depends on the structure of the code. We show that its success also depends on the size of row and column weights. Matrix space restriction is another technique that can be applied to any code and has fixed reduction in time or amount of overlap. Its success depends on the amount of restriction and may be traded with performance loss. The third technique already suggested in literature relies on the internal cyclic structure of sub-matrices to achieve overlapping. The technique is limited to LDPC code matrices in which the number of sub-matrices is equal to row and column weights. We show that it can be applied to other codes with a lager number of sub-matrices than code weights. However, in this case maximum overlap is not guaranteed. We calculate the lower bound on the amount of overlapping. Overlapping could be applied to any sub-matrix configuration of quasi-cyclic codes by arbitrarily choosing \nthe starting rows for processing. Overlapping decoding time depends on inter-iteration waiting times. We show that there are upper bounds on waiting times which depend on the code weights. Waiting times could be further reduced by restricting shifts in identity sub-matrices or using smaller sub-matrices. This overlapping technique can reduce the decoding time by up to 50% compared to conventional message and computation scheduling. \nTechniques of matrix permutation and space restriction results in decoder architectures that are flexible in LDPC code design in terms of code weights and size. This is due to the fact that with these techniques, rows and columns are processed in sequential order to achieve overlapping. However, in the existing technique, all sub-matrices have to be processed in parallel to achieve overlapping. Parallel processing of all code sub-matrices requires the architecture to have the number of processing units at least equal to the number sub-matrices. Processing units and memory space should therefore be distributed among the sub-matrices according to the sub-matrices arrangement. This leads to high complexity or inflexibility in the decoder architecture. We propose a simple, programmable and high throughput decoder architecture based on matrix permutation and space restriction techniques.