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Design of two-edge type LDPC codes with high rate and short length

Mi Xiao

Published Jan 1, 2014• 0 citations
OpenAlex

Abstract

It is a challenge to design high-rate LDPC codes,especially with short length. Two-edge type LDPC( TET-LDPC) codes proposed recently have been shown to possess better performance than conventional LDPC codes at high rate. In this paper,structural advantages of TET-LDPC codes are investigated. Based on the advantages,a novel approach to design TET-LDPC codes at high rate is proposed,which aims to improve the performance by choosing a suitable degree for punctured variable nodes and optimizing the connections between variable nodes and check nodes. The simulation results show that the short-length high-rate TET-LDPC codes designed by the proposed approach can not only outperform conventional LDPC codes and conventional TET-LDPC codes,but also have lower error floors.

Related papers

Design of Finite-Length Generalized LDPC Codes

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Finding coding schemes that approach the Shannon capacity limit has been the central theme during the development of error-control coding (ECC).In recent years low-density parity-check (LDPC) codes, due to their remarkable performance under iterative decoding, have received extensive study and have been adopted by many modern advanced communication systems.LDPC codes can be further extended to generalized LDPC (GLDPC) codes and doublygeneralized LDPC (DGLDPC) codes.GLDPC and DGLDPC codes are supersets of LDPC codes that possess more generic code structures.GLDPC and DGLDPC codes are more flexible than LDPC codes, since a richer variety of check nodes (CNs) or variable nodes (VNs) offers additional options and flexibility, which enable many advantages over LDPC codes in numerous scenarios.In this dissertation we focus on improved design methods for finite-length (FL) GLDPC and DGLDPC codes.The first research topic is the error floor behavior of FL-GLDPC and FL-DGLDPC codes.In GLDPC and DGLDPC codes, the existence of generalized CNs and VNs requires more careful management of edge connections for achieving low error floors.In this work the approximate cycle extrinsic message degree (ACE), a cycle parameter used in LDPC codes that reflects the resilience of the cycle to the noise, is generalized to extended ACE (eACE) for GLDPC and DGLDPC codes.By integrating eACE into the progressive-edge-growth (PEG) algorithm and adding more constraints on the connectivity of nodes, the error floor performance of GLDPC and DGLDPC codes can be greatly improved.In practice, designing codes capable of fast encoding is an important issue.Efficiently-encodable (EE) GLDPC and DGLDPC codes are studied and a self-consistent unified framework is proposed for constructing EE iteratively-decodable block codes, including EE-LDPC, EE-GLDPC and EE-DGLDPC codes.The competing nature of the fast encoding speed and the low error floor performance iv Abstract v is analyzed and verified via various simulation results.EE codes are systematic and suitable for puncturing; therefore, they are good candidates for rate-compatible (RC) data transmissions.Based on the characteristics of GLDPC and DGLDPC codes, we devise several systematic puncturing algorithms to provide good puncturing patterns for them.It is shown that we can significantly improve the code performance compared with random puncturing.Over a wide range of code rates, RC EE-GLDPC and EE-DGLDPC codes show advantages over EE-LDPC codes, especially at high signal-to-noise ratios (SNRs).

•Apr 30, 2013•0 citations

Efficient Design of Structured LDPC Codes

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Studies on Lowering the Error Floors of Finite Length LDPC codes

Huanlin Li

Low-density parity-check (LDPC) codes can approach the Shannon limit performance closely, and are becoming one of the most promising channel codes in the Error Control Coding area.The performance of an LDPC code with given length is mainly affected by the sizes of some combinatorial characteristics of its corresponding bipartite graph and the distribution of variable degrees and check node degrees.With the help of the density evolution algorithm, randomly designed LDPC codes, with carefully chosen degree distribution pairs, have been shown to achieve better Shannon capacity performance than their regular counterparts when decoded using the iterative belief propagation (BP) decoding algorithm.However, regular LDPC codes outperform their irregular counterparts in term of their error floors.Therefore, construction of LDPC codes which have both attractive error rate performance and low error floor performance has become an attractive topic.Currently, optimization of variable node degree distribution and check node degree distribution for an LDPC code with given length, which could help the code to achieve good Shannon limit performance, has been extensively studied.In this dissertation, we demonstrate some approaches of improving the error floor performance for a given LDPC code with desired degree distribution pair.The contribution mainly includes three parts.In the first part, the relationship between cycles and unfavorable combinatorial

•Jan 1, 2011•0 citations
It is a challenge to design high-rate LDPC codes,especially with short length. Two-edge type LDPC( TET-LDPC) codes proposed recently have been shown to possess better performance than conventional LDPC codes at high rate. In this paper,structural advantages of TET-LDPC codes are investigated. Based on the advantages,a novel approach to design TET-LDPC codes at high rate is proposed,which aims to improve the performance by choosing a suitable degree for punctured variable nodes and optimizing the connections between variable nodes and check nodes. The simulation results show that the short-length high-rate TET-LDPC codes designed by the proposed approach can not only outperform conventional LDPC codes and conventional TET-LDPC codes,but also have lower error floors.
Finding coding schemes that approach the Shannon capacity limit has been the central theme during the development of error-control coding (ECC).In recent years low-density parity-check (LDPC) codes, due to their remarkable performance under iterative decoding, have received extensive study and have been adopted by many modern advanced communication systems.LDPC codes can be further extended to generalized LDPC (GLDPC) codes and doublygeneralized LDPC (DGLDPC) codes.GLDPC and DGLDPC codes are supersets of LDPC codes that possess more generic code structures.GLDPC and DGLDPC codes are more flexible than LDPC codes, since a richer variety of check nodes (CNs) or variable nodes (VNs) offers additional options and flexibility, which enable many advantages over LDPC codes in numerous scenarios.In this dissertation we focus on improved design methods for finite-length (FL) GLDPC and DGLDPC codes.The first research topic is the error floor behavior of FL-GLDPC and FL-DGLDPC codes.In GLDPC and DGLDPC codes, the existence of generalized CNs and VNs requires more careful management of edge connections for achieving low error floors.In this work the approximate cycle extrinsic message degree (ACE), a cycle parameter used in LDPC codes that reflects the resilience of the cycle to the noise, is generalized to extended ACE (eACE) for GLDPC and DGLDPC codes.By integrating eACE into the progressive-edge-growth (PEG) algorithm and adding more constraints on the connectivity of nodes, the error floor performance of GLDPC and DGLDPC codes can be greatly improved.In practice, designing codes capable of fast encoding is an important issue.Efficiently-encodable (EE) GLDPC and DGLDPC codes are studied and a self-consistent unified framework is proposed for constructing EE iteratively-decodable block codes, including EE-LDPC, EE-GLDPC and EE-DGLDPC codes.The competing nature of the fast encoding speed and the low error floor performance iv Abstract v is analyzed and verified via various simulation results.EE codes are systematic and suitable for puncturing; therefore, they are good candidates for rate-compatible (RC) data transmissions.Based on the characteristics of GLDPC and DGLDPC codes, we devise several systematic puncturing algorithms to provide good puncturing patterns for them.It is shown that we can significantly improve the code performance compared with random puncturing.Over a wide range of code rates, RC EE-GLDPC and EE-DGLDPC codes show advantages over EE-LDPC codes, especially at high signal-to-noise ratios (SNRs).
The high encoding complexity of LDPC codes can be solved by designing structured parity-check matrix. If the parity-check matrix of LDPC codes is composed of same type of blocks, decoder implementation can be simple, this structure allow structured decoding and required memory for storing the parity-check matrix can be reduced largely. In this paper, we propose a construction algorithm for short block length structured LDPC codes based on girth condition, PEG algorithm and variable node connectivity. The code designed by this algorithm shows similar performance to other codes without structured constraint in low SNR and better performance in high SNR than those by simulation
Short-length scale-free low-density-paritycheck (SF-LDPC) codes have been found to outperform codes optimized by the density-evolution technique. However, a large fraction of degree-2 variable nodes will exist in SF-LDPC codes when the code rate is high. Consequently, small-size cycles with no external connections can easily be created by these degree-2 nodes, producing a large error rate. In this paper, we propose constraining the proportion of degree-2 variable nodes in the design SF-LDPC codes. We will evaluate the error performance of the high-rate SFLDPC codes under the new constraint.
This paper proposes two new cycle-optimized algorithms, called the multi-step progressive edge-growth (PEG) algorithm and the multi-step approximate cycle extrinsic message degree (ACE) constrained PEG algorithm, to design an LDPC code with larger girth and better cycle-connectivity. In addition, an efficient method is developed to calculate the distances between the variable nodes (VNs) and the check nodes (CNs) in the proposed algorithms. Simulation results show that compared to the conventional cycle-optimized algorithms, the proposed algorithms can achieve both better cycle-connectivity and foreseeable lower error floors.
In this paper we design protograph-based LDPC codes with short block sizes. Mainly we consider rate 1/2 codes with input block sizes 64, 128, and 256 bits. To simplify the encoder and decoder implementations for high data rate transmission, the structure of the codes is based on protographs and circulants. These codes are designed for short block sizes based on maximizing the minimum distance and stopping set size subject to a constraint on the maximum variable node degree. In particular, we consider codes with variable node degrees between 3 and 5. Increasing the node degree leads to larger minimum distances, at the expense of smaller girth. Therefore, there is a trade-off between undetected error rate performance (improved by increasing minimum distance) and the degree of sub-optimality of the iterative decoders typically used (which are adversely affected by graph loops). Various LDPC codes are compared and simulation results are provided.
Low-density parity-check (LDPC) codes can approach the Shannon limit performance closely, and are becoming one of the most promising channel codes in the Error Control Coding area.The performance of an LDPC code with given length is mainly affected by the sizes of some combinatorial characteristics of its corresponding bipartite graph and the distribution of variable degrees and check node degrees.With the help of the density evolution algorithm, randomly designed LDPC codes, with carefully chosen degree distribution pairs, have been shown to achieve better Shannon capacity performance than their regular counterparts when decoded using the iterative belief propagation (BP) decoding algorithm.However, regular LDPC codes outperform their irregular counterparts in term of their error floors.Therefore, construction of LDPC codes which have both attractive error rate performance and low error floor performance has become an attractive topic.Currently, optimization of variable node degree distribution and check node degree distribution for an LDPC code with given length, which could help the code to achieve good Shannon limit performance, has been extensively studied.In this dissertation, we demonstrate some approaches of improving the error floor performance for a given LDPC code with desired degree distribution pair.The contribution mainly includes three parts.In the first part, the relationship between cycles and unfavorable combinatorial