Forthcoming CMOS technology nodes are in principle sufficient for achieving both the quantum information density and the speed that are critical for error-free logical qubits. Using data from the roadmap for semiconductor devices from ITRS and IEDM, we applied the standard CMOS design rules to a universal set of quantum logic gates to control silicon qubits. We consequently obtain a scaling law for quantum information density for Steane code, concatenated codes, and surface code, which represent the quantum information equivalent of Moore's law in terms of density scaling per node. By imposing the constraints due to both quantum error correction and the intrinsic operation speed limitation of a physical silicon qubit, we determine that technology nodes below 14 nm can in principle support error-free logical qubits manipulated at GHz frequency. We review the current state-of- the-art of silicon technology to assess the performance of different silicon qubit architectures based on CMOS single donors and double quantum dot devices. Our analysis demonstrates that silicon technology is compatible with the scalability requirements imposed by quantum error correction architectures for universal quantum computing. Such considerations provide a benchmark for the development of a silicon-based quantum computer and a general guideline for other quantum technology platforms.
Forthcoming CMOS technology nodes are in principle sufficient for achieving both the quantum information density and the speed that are critical for error-free logical qubits. Using data from the roadmap for semiconductor devices from ITRS and IEDM, we applied the standard CMOS design rules to a universal set of quantum logic gates to control silicon qubits. We consequently obtain a scaling law for quantum information density for Steane code, concatenated codes, and surface code, which represent the quantum information equivalent of Moore's law in terms of density scaling per node. By imposing the constraints due to both quantum error correction and the intrinsic operation speed limitation of a physical silicon qubit, we determine that technology nodes below 14 nm can in principle support error-free logical qubits manipulated at GHz frequency. We review the current state-of- the-art of silicon technology to assess the performance of different silicon qubit architectures based on CMOS single donors and double quantum dot devices. Our analysis demonstrates that silicon technology is compatible with the scalability requirements imposed by quantum error correction architectures for universal quantum computing. Such considerations provide a benchmark for the development of a silicon-based quantum computer and a general guideline for other quantum technology platforms.
Abstract Even the quantum simulation of an apparently simple molecule such as Fe2S2requires a considerable number of qubits of the order of 106, while more complex molecules such as alanine (C3H7NO2) require about a hundred times more. In order to assess such a multimillion scale of identical qubits and control lines, the silicon platform seems to be one of the most indicated routes as it naturally provides, together with qubit functionalities, the capability of nanometric, serial, and industrial-quality fabrication. The scaling trend of microelectronic devices predicting that computing power would double every 2 years, known as Moore’s law, according to the new slope set after the 32-nm node of 2009, suggests that the technology roadmap will achieve the 3-nm manufacturability limit proposed by Kelly around 2020. Today, circuital quantum information processing architectures are predicted to take advantage from the scalability ensured by silicon technology. However, the maximum amount of quantum information per unit surface that can be stored in silicon-based qubits and the consequent space constraints on qubit operations have never been addressed so far. This represents one of the key parameters toward the implementation of quantum error correction for fault-tolerant quantum information processing and its dependence on the features of the technology node. The maximum quantum information per unit surface virtually storable and controllable in the compact exchange-only silicon double quantum dot qubit architecture is expressed as a function of the complementary metal–oxide–semiconductor technology node, so the size scale optimizing both physical qubit operation time and quantum error correction requirements is assessed by reviewing the physical and technological constraints. According to the requirements imposed by the quantum error correction method and the constraints given by the typical strength of the exchange coupling, we determine the workable operation frequency range of a silicon complementary metal–oxide–semiconductor quantum processor to be within 1 and 100 GHz. Such constraint limits the feasibility of fault-tolerant quantum information processing with complementary metal–oxide–semiconductor technology only to the most advanced nodes. The compatibility with classical complementary metal–oxide–semiconductor control circuitry is discussed, focusing on the cryogenic complementary metal–oxide–semiconductor operation required to bring the classical controller as close as possible to the quantum processor and to enable interfacing thousands of qubits on the same chip via time-division, frequency-division, and space-division multiplexing. The operation time range prospected for cryogenic control electronics is found to be compatible with the operation time expected for qubits. By combining the forecast of the development of scaled technology nodes with operation time and classical circuitry constraints, we derive a maximum quantum information density for logical qubits of 2.8 and 4 Mqb/cm2for the 10 and 7-nm technology nodes, respectively, for the Steane code. The density is one and two orders of magnitude less for surface codes and for concatenated codes, respectively. Such values provide a benchmark for the development of fault-tolerant quantum algorithms by circuital quantum information based on silicon platforms and a guideline for other technologies in general.
Recent advances in quantum error correction codes for fault-tolerant quantum computing and physical realizations of high-fidelity qubits in multiple platforms give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based on complementary metal-oxide-semiconductor (CMOS) technology. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin state of a single electron confined in quantum dots, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout. We implement a spin qubit surface code, showing the prospects for universal quantum computation. We discuss the challenges and focus areas that need to be addressed, providing a path for large-scale quantum computing.
Abstract Recent advances in quantum error correction codes for fault-tolerant quantum computing and physical realizations of high-fidelity qubits in multiple platforms give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based on complementary metal-oxide-semiconductor (CMOS) technology. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin state of a single electron confined in quantum dots, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout. We implement a spin qubit surface code, showing the prospects for universal quantum computation. We discuss the challenges and focus areas that need to be addressed, providing a path for large-scale quantum computing.
Abstract Quantum computation (QC) is one of the most challenging quantum technologies that promise to revolutionize data computation in the long-term by outperforming the classical supercomputers in specific applications. Errors will hamper this quantum revolution if not sufficiently limited and corrected by quantum error correction codes thus avoiding quantum algorithm failures. In particular millions of highly-coherent qubits arranged in a two-dimensional array are required to implement the surface code, one of the most promising codes for quantum error correction. One of the most attractive technologies to fabricate such large number of almost identical high-quality devices is the well known metal-oxide-semiconductor technology. Silicon quantum processor manufacturing can leverage the technological developments achieved in the last 50 years in the semiconductor industry. Here, we review modeling, fabrication aspects and experimental figures of merit of qubits defined in the spin degree of freedom of charge carriers confined in quantum dots and donors in silicon devices along with classical electronics innovations for qubit control and readout. Furthermore, we discuss potential applications of the technology and finally we review the role of start-ups and companies in the silicon-based QC era.
Quantum computers require a coordinated operation on a large number of quantum bits (qubits), presenting considerable obstacles such as system integration on a large scale, individual qubits control with precision, and significant error correction overhead. Silicon (Si) quantum dot (QD) spin qubits paired with CMOS control circuits promise a scalable solution due to its potential for large-scale integration utilizing well-established semiconductor technologies. This paper proposes a control addressing scheme for QD spin qubits operating on a node network architecture. Compared to the typical 2-dimensional array architecture, this approach considerably lowers the area constraint for control signal routing. Scalable circuits are designed to route the control signals for local and global operations of a surface code quantum error correction through the modular design of tiered switches controlled by demultiplexers. The proposed method is a critical step toward implementing scalable solid-state quantum processors.
Commercially-relevant quantum computers will require large numbers of high-performing qubits that can be manufactured, integrated, and controlled at scale. Silicon exchange-only (EO) qubits are a strong candidate modality due to their control-signal simplicity and compatibility with advanced semiconductor manufacturing, but questions remain around the achievability of sufficiently low noise and a scalable control and wiring solution. Here we introduce a quantum processing unit composed of a custom-designed cryogenic CMOS controller, a novel high-density superconducting ribbon cable, and a low-noise EO qubit device. The quantum chip features a three-rail array of 54 exchange-coupled quantum dots, configurable to host up to 18 EO qubits. We integrate and use these components to demonstrate qubit performance for both single-qubit and entangling operations that advances the EO state of the art by an order of magnitude. We further validate this system by implementing a distance-5 repetition code and a quantum error detecting code then make detailed comparisons with simulations. Our approach facilitates a utility-scale quantum computer with manageable operational and capital requirements.