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arXiv:2604.16216 · Nature

A digitally controlled silicon quantum processing unit

Members of the HRL Quantum Team, Collaborators, :, Michael Abraham, Edwin Acuna, Tower S. Adams, Moonmoon Akmal, Matthew R. Alfaro, I. Alvarado, Jacob Amontree, Carter Andrews, Reed W. Andrews, Michael Antcliffe, Andre R. Aséncio, Ryan M. Avila Batres, Cynthia D. Baringer, David W. Barnes, Katherine M. Beech, Russell G. Blakey, Zachery T. Bloom, Aaron J. Bluestone, Jacob Z. Blumoff, Matthew G. Borselli, Koel A. Bose, Brydon Boyd, Jacob T. Boyer, Teresa L. Brecht, Christopher C. Brough, Rex A. Brown, Steven L. Brown, Tyler A. Cain, John B. Carpenter, Stephen Carr, Faustin W. Carter, Mitchell Casanova, Jacob L. Chambers, Matthew D. Chambers, Khamsorn L. Chanthavong, James M. Chappell, Rhian Chavez, Kevin C. Chen, Peter S. Chen, Maxwell D. Choi, Krishna Choudhary, Matthew N. H. Chow, Justin E. Christensen, Aaron M. Chronister, Andrew M. Clapper, Abigail A. Coker, Michael D. Cornelius, Albert E. Cosand, Ian T. Counts, Edward T. Croke, Gregory M. Crosswhite, Adam Dally, Erik S. Daniel, Tuan A. Dao, Dominic Daprano, Tiffany Davis, Neha Deshpande, Rachel S. Dey, D. Scott Diamond, Claire E. Dickerson, J. P. Dodson, James B. Dragan, Marc Dvorak, Lisa F. Edge, Charles R. Elliott, Kenneth R. Elliott, Kevin Eng, Jacob Fast, Colin P. Feeney, David J. Fialkow, Dylan H. Finestone, Micha N. Fireman, Bryan H. Fong, Trevor M. Fowler, Sean Frazier, Kiera L. Fuller, Christina A. C. Garcia, Kacy L. Garstka, Kara C. Garvey, Zachary A. Geiger, Galen R. Gledhill, Caleigh M. Goodwin-Schoen, Joseph L. Goralka, Bradley W. Greene, Hrayr K. Gurgenian, Sieu D. Ha, Wonill Ha, Nathanial R. Hapeman, Brooke M. Hardesty, Jim W. Harrington, Patrick M. Harrington, Thomas R. B. Harris, Ben M. Harrison, Anthony T. Hatke, Robert R. Hayes, Kevin He, Raul Hernandez Garcia, Ryan M. Hickey, Jocelyn Hicks-Garner, Alex Hirman, Donald A. Hitko, David Ho, Holland Y. Ho, Vinh S. Ho, nathan holman, Adam Holmes, Nerys Huffman, Daniel R. Hulbert, Eric B. Isaacs, Clayton A. C. Jackson, Logan Jaeger, Ian Jenkins, Cameron Jennings, Paul C. Jerger, B. Johnson, Aaron M. Jones, Michael P. Jura, Adour V. Kabakian, Raj M. Katti, Tyler Keating, Joseph Kerckhoff, Joseph D. Kern, Isaac Khalaf, Aditya Kher, Jake J. Kim, Erich W. Kinder, Andrey A. Kiselev, William F. Koehl, Patrick W. Krantz, Thaddeus D. Ladd, Pierce G. Laing, Sanaaya Lakdawala, Nathan J. Lang, Robert Lanza, Elias Lawson-Fox, Dustin Le, Kangmu Lee, Nathan R. A. Lee, Jaime Lerma, Mark P. Levendorf, Alwina R. Liu, Henry Lizarraga, Aurelio Lopez, Hoa C. Ly, Torrey T. Lyons, Theodore K. Macioce, Matthew M. Mackey, John K. Maeda, Ryan M. Martin, Daniel S. Matic, Justine W. Matten, Gavin C. Mazur, Max S. McCready, Olivia Means, Kevin E. Millner, Ivan Milosavljevic, Matthew Morris, Susan L. Morton, Samuel Mumford, Bryce D. Murley, Robert G. Nagele, Taro A. Naoi, Cameron R. Nelson, Georgia A. Newman, David B. Nguyen, Tina Niknejad, Rebecca N. Nishide, Liam C. O'Brien, Colin B. E. O'Keefe, Riley P. O'Neil, Andrew E. Oriani, Anthony F. Ortiz, John J. Ottusch, Andrew Pan, Pamela R. Patterson, Uttam Paudel, Julius C. Perez, Christi A. Peterson, Vu T. Phan, Nickolas H. Pilgram, Clifford E. Plesha, Winston Pouse, Eric M. Prophet, Daniel R. Queen, Nicholas Quirk, Kate Raach, Matthew T. Rakher, Matthew D. Reed, Brandon D. Reynolds, Luke D. Robertson, Zechariah Rogers, Yakov Royter, Matthew J. Ruiz, Golam Sabbir, Roshan Sajjad, Christopher D. Sanborn, Rachel H. Sarmiento, Christian J. Schnaible, Cole Scott, Nicholas M. Sebastiani, Eric M. Segall, Alen Senanian, Adalberto Sicairos, Shariq Siddiqui, Kartik Singh, Aaron Smith, Daniel E. Smith, Robert S. Smith, Sarah F. Sontag, Emilio A. Sovero, Kevin C. Staley, Andrea Su, June Suh, Bo Sun, Danny Sun, Christopher M. Swank, Noah Swimmer, Mariano J. Taboada, Bryan J. Thomas, Yessica Torres, Jeremy W. Touve, Alan Tran, Ivan Tran, Chantang Tsen, Skylar Turner, Miguel Valencia, Irma Valles, James R. van Meter, Nicholas D. VanRensselaer, Franklin Vartanian, Daniel Volya, Zachary J. Vrba, Phuong Hong Vu, Annette L. Wagner, John Wallner, Michael P. Walsh, Shuoqin Wang, Tong Wang, Daniel R. Ward, Aaron J. Weinstein, Terry B. Welch, Thomas V. Westrick, Evan T. White, Randall M. White, Samuel J. Whiteley, Gananath Wijeratne, Parker Williams, Jack T. Wilson, Courtney P. Wilt, Deborah E. Winklea, Onnik Yaglioglu, Daniel Yap, Clifford S. YoungSciortino, Daniel Zehnder, Andrew Ziegler

quant-phSubmitted Apr 17, 2026• Announced Apr 20, 2026• 5 citations• Revised May 1, 2026 (v2)
v1 · Apr 17, 2026v2 · May 1, 2026
arXivHTMLPDF

Abstract

Commercially-relevant quantum computers will require large numbers of high-performing qubits that can be manufactured, integrated, and controlled at scale. Silicon exchange-only (EO) qubits are a strong candidate modality due to their control-signal simplicity and compatibility with advanced semiconductor manufacturing, but questions remain around the achievability of sufficiently low noise and a scalable control and wiring solution. Here we introduce a quantum processing unit composed of a custom-designed cryogenic CMOS controller, a novel high-density superconducting ribbon cable, and a low-noise EO qubit device. The quantum chip features a three-rail array of 54 exchange-coupled quantum dots, configurable to host up to 18 EO qubits. We integrate and use these components to demonstrate qubit performance for both single-qubit and entangling operations that advances the EO state of the art by an order of magnitude. We further validate this system by implementing a distance-5 repetition code and a quantum error detecting code then make detailed comparisons with simulations. Our approach facilitates a utility-scale quantum computer with manageable operational and capital requirements.

Journal reference
Nature 655, 1154 2026
DOI
10.1038/s41586-026-10754-7

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Commercially-relevant quantum computers will require large numbers of high-performing qubits that can be manufactured, integrated, and controlled at scale. Silicon exchange-only (EO) qubits are a strong candidate modality due to their control-signal simplicity and compatibility with advanced semiconductor manufacturing, but questions remain around the achievability of sufficiently low noise and a scalable control and wiring solution. Here we introduce a quantum processing unit composed of a custom-designed cryogenic CMOS controller, a novel high-density superconducting ribbon cable, and a low-noise EO qubit device. The quantum chip features a three-rail array of 54 exchange-coupled quantum dots, configurable to host up to 18 EO qubits. We integrate and use these components to demonstrate qubit performance for both single-qubit and entangling operations that advances the EO state of the art by an order of magnitude. We further validate this system by implementing a distance-5 repetition code and a quantum error detecting code then make detailed comparisons with simulations. Our approach facilitates a utility-scale quantum computer with manageable operational and capital requirements.
Abstract The most promising quantum algorithms require quantum processors that host millions of quantum bits when targeting practical applications1. A key challenge towards large-scale quantum computation is the interconnect complexity. In current solid-state qubit implementations, an important interconnect bottleneck appears between the quantum chip in a dilution refrigerator and the room-temperature electronics. Advanced lithography supports the fabrication of both control electronics and qubits in silicon using technology compatible with complementary metal oxide semiconductors (CMOS)2. When the electronics are designed to operate at cryogenic temperatures, they can ultimately be integrated with the qubits on the same die or package, overcoming the ‘wiring bottleneck’3–6. Here we report a cryogenic CMOS control chip operating at 3 kelvin, which outputs tailored microwave bursts to drive silicon quantum bits cooled to 20 millikelvin. We first benchmark the control chip and find an electrical performance consistent with qubit operations of 99.99 per cent fidelity, assuming ideal qubits. Next, we use it to coherently control actual qubits encoded in the spin of single electrons confined in silicon quantum dots7–9 and find that the cryogenic control chip achieves the same fidelity as commercial instruments at room temperature. Furthermore, we demonstrate the capabilities of the control chip by programming a number of benchmarking protocols, as well as the Deutsch–Josza algorithm10, on a two-qubit quantum processor. These results open up the way towards a fully integrated, scalable silicon-based quantum computer.
Solid-state quantum computers require classical electronics to control and readout individual qubits and to enable fast classical data processing [1-3]. Integrating both subsystems at deep cryogenic temperatures [4], where solid-state quantum processors operate best, may solve some major scaling challenges, such as system size and input/output (I/O) data management [5]. Spin qubits in silicon quantum dots (QDs) could be monolithically integrated with complementary metal-oxide-semiconductor (CMOS) electronics using very-large-scale integration (VLSI) and thus leveraging over wide manufacturing experience in the semiconductor industry [6]. However, experimental demonstrations of integration using industrial CMOS at mK temperatures are still in their infancy. Here we present a cryogenic integrated circuit (IC) fabricated using industrial CMOS technology that hosts three key ingredients of a silicon-based quantum processor: QD arrays (arranged here in a non-interacting 3x3 configuration), digital electronics to minimize control lines using row-column addressing and analog LC resonators for multiplexed readout, all operating at 50 mK. With the microwave resonators (6-8 GHz range), we show dispersive readout of the charge state of the QDs and perform combined time- and frequency-domain multiplexing, enabling scalable readout while reducing the overall chip footprint. This modular architecture probes the limits towards the realization of a large-scale silicon quantum computer integrating quantum and classical electronics using industrial CMOS technology.
Quantum computing promises to revolutionize our lives, achieving unprecedented computational powers and unlocking new possibilities in drug discovery, chemical simulations and cryptography. The fundamental unit of computation of a quantum computer is the quantum bit (qubit). It can be implemented in a number of technologies, such as superconducting qubits, spin qubits, photonic systems, trapped ions and NV-centers. Solid-state superconducting qubits and spin qubits seem to be the most promising ones, as shown by the recent demonstration of quantum supremacy with a superconducting qubit processor. Such quantum processors, to operate in the quantum regime, require very low temperatures around 10 mK, and they are hence kept inside dilution fridges. The electronics required to read out and control such processors is typically realized by discrete components or bulky scientific instruments at room temperature wired into the dilution fridge. Such approach is only feasible until few (< 100) qubits are handled, but it is not scalable for million-qubit processors required for fault-tolerant operation. In this thesis, readout and control electronics is proposed to be integrated and operated directly at cryogenic temperatures, in close proximity with the qubits and potentially even co-integrated. CMOS technology is advocated for its scalability, compactness and low prototyping cost, to create a comprehensive cryo-CMOS class of fully-integrated transceivers to read out and control solid-state qubits. In particular, the thesis focuses on cryo-CMOS radio-frequency integrated circuits for the readout of silicon quantum computers, looking to integrate the whole readout system, from the quantum layer to the room temperature user interface. Cryogenic CMOS devices are explored first, to lay the foundations of integrated circuit design. The realization of quantum dots in standard CMOS technology is explored as a platform to realize solid-state qubit arrays, demonstrating functionality at 50 mK and good reproducibility. Moreover, the operation of integrated transistors at 50 mK and 4.2 K is explored to understand their basic cryogenic functionality, through characterization and modeling. Then also integrated passives, such as capacitors, inductors and transformers, are studied and modeled at cryogenic temperatures. Then, a fully-integrated readout platform spanning across all the blocks needed for dispersive readout is proposed. A fully-integrated matrix of quantum dots with radio-frequency gate-based readout capabilities is demonstrated along with time- and frequency-multiplexing. This quantum-classical circuit shows all the features for a scalable approach and is the core of the platform following it. A cryogenic CMOS circulator based on a new all-pass filter architecture is demonstrated, to be used as integrated replacement for current bulky counterparts; it allows power reduction, insertion loss and bandwidth enhancement with respect to state-of-the-art integrated circulators. The rest of the front-end is also explored with dedicated test multiplexers, a low noise-amplifier and an oscillator, that are finally merged in a single fully-integrated low-noise receiver with frequency synthesizer operating at 3.5 K for scalable multiplexed readout of silicon qubits. The platform presented in this thesis, across temperature boundaries, carries all the features required for future scalable silicon quantum computing platforms and could therefore form their core.
Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'. In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator. Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended. In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K. We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures. One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.
A scaled-up quantum computer will require a highly efficient control interface that autonomously manipulates and reads out large numbers of qubits, which for solid-state implementations are usually held at millikelvin (mK) temperatures. Advanced CMOS technology, tightly integrated with the quantum system, would be ideal for implementing such a control interface but is generally discounted on the basis of its power dissipation that leads to heating of the fragile qubits. Here, we demonstrate an ultra low power, CMOS-based quantum control platform that takes digital commands as input and generates many parallel qubit control signals. Realized using 100,000 transistors operating near 100 mK, our platform alleviates the need for separate control lines to every qubit by exploiting the low leakage of transistors at cryogenic temperatures to store charge on floating gate structures that are used to tune-up quantum devices. This charge can then be rapidly shuffled between on-chip capacitors to generate the fast voltage pulses required for dynamic qubit control. We benchmark this architecture on a quantum dot test device, showing that the control of thousands of gate electrodes is feasible within the cooling power of commercially available dilution refrigerators.
Quantum chips form the foundational hardware for quantum computing, promising transformative impacts across optimization, secure communications, and artificial intelligence. This paper surveys five leading qubit implementations—superconducting circuits, neutral-atom arrays, trapped ions, photonic systems, and silicon-based quantum dots—highlighting their distinct operating principles, recent milestones, and inherent trade-offs. Superconducting platforms leverage mature microfabrication to achieve hundreds to thousands of qubits with rapid gate times but require millikelvin environments and face millisecond-scale coherence limits. Neutral-atom and ion-trap architectures offer exceptionally long coherence (seconds to hours) and high-fidelity operations, making them ideal for quantum memory and precision simulation, yet scaling remains constrained by control complexity. Photonic chips excel at room-temperature operation and quantum networking via entangled photons, though deterministic two-qubit gates and on-chip integration pose challenges. Silicon quantum dots promise CMOS compatibility and sub-microsecond spin coherence, but demand atomic-scale fabrication precision and advanced cryogenic control. We analyze the tension between qubit count, error rates, and engineering practicality, and discuss emerging solutions such as hybrid integration, advanced error-correction codes, and novel materials. Looking ahead, coordinated optimization across these platforms—combining fast superconducting processors, long-lived atomic memories, photonic interconnects, and scalable silicon arrays—will be critical to transition quantum chips from research prototypes to industrially viable systems that redefine computing, communications, and AI.