A quantum computer can solve fundamentally difficult problems by utilizing properties of quantum bits (qubits). It consists of a quantum substrate, connected to a conventional computer, termed as control processor. A control processor can manipulate and measure the state of the qubits and act as an interface between qubits and the programmer. Unfortunately, qubits are extremely noise-sensitive, and to minimize the noise; qubits are operated at cryogenic temperatures. To build a scalable quantum computer, a control processor which can work at cryogenic temperatures is essential [3, 14]. In this paper, we focus on the challenges of building a memory system for a cryogenic control processor. A scalable quantum computer will require large memory capacity for storing the program and the data generated by the quantum error correction. To this end, we evaluate the feasibility of cryogenic DRAM-based memory system by characterizing commercial DRAM modules at cryogenic temperatures. In this paper, we report the minimum operational temperature for 55 DIMMs (consisting of a total of 750 DRAM chips) and analyze the error patterns in commodity DRAM devices operated at cryogenic temperatures. Our study shows that a significant fraction of DRAM chips continue to work at temperatures as low as 80K. This study is an initial step towards evaluating the effectiveness of cryogenic DRAM as a main memory for quantum computers.
A quantum computer can solve fundamentally difficult problems by utilizing properties of quantum bits (qubits). It consists of a quantum substrate, connected to a conventional computer, termed as control processor. A control processor can manipulate and measure the state of the qubits and act as an interface between qubits and the programmer. Unfortunately, qubits are extremely noise-sensitive, and to minimize the noise; qubits are operated at cryogenic temperatures. To build a scalable quantum computer, a control processor which can work at cryogenic temperatures is essential [3, 14]. In this paper, we focus on the challenges of building a memory system for a cryogenic control processor. A scalable quantum computer will require large memory capacity for storing the program and the data generated by the quantum error correction. To this end, we evaluate the feasibility of cryogenic DRAM-based memory system by characterizing commercial DRAM modules at cryogenic temperatures. In this paper, we report the minimum operational temperature for 55 DIMMs (consisting of a total of 750 DRAM chips) and analyze the error patterns in commodity DRAM devices operated at cryogenic temperatures. Our study shows that a significant fraction of DRAM chips continue to work at temperatures as low as 80K. This study is an initial step towards evaluating the effectiveness of cryogenic DRAM as a main memory for quantum computers.
Quantum computation has been a major focus of research in the past two decades, with recent experiments demonstrating basic algorithms on small numbers of qubits. A large-scale universal quantum computer would have a profound impact on science and technology, providing a solution to several problems intractable for classical computers. To realise such a machine, today's small experiments must be scaled up, and a system must be built which provides control and measurement of many hundreds of qubits. A device of this scale is challenging: qubits are highly sensitive to their environment, and sophisticated isolation techniques are required to preserve the qubits' fragile states. Solid-state qubits require deep-cryogenic cooling to suppress thermal excitations. Yet current state-of-the-art experiments use room-temperature electronics which are electrically connected to the qubits. This thesis investigates various scalable technologies and techniques which can be used to control quantum systems. With the requirements for semiconductor spin-qubits in mind, several custom electronic systems, to provide quantum control from deep cryogenic temperatures, are designed and measured. A system architecture is proposed for quantum control, providing a scalable approach to executing quantum algorithms on a large number of qubits. Control of a gallium arsenide qubit is demonstrated using a cryogenically operated FPGA driving custom gallium arsenide switches. The cryogenic performance of a commercial FPGA is measured, as the main logic processor in a cryogenic quantum control system, and digital-to-analog converters are analysed during cryogenic operation. Recent work towards a 100-qubit cryogenic control system is shown, including the design of interconnect solutions and multiplexing circuitry. With qubit fidelity over the fault-tolerant threshold for certain error correcting codes, accompanying control platforms will play a key role in the development of a scalable quantum machine.
Quantum computers consist of a quantum processor – sets of quantum bits or qubits operating at an extremely low temperature – and a classical electronic controller to read out and control the processor. The machines utilize the unusual properties of matter at extremely small scales – the fact that a qubit, can represent “1” and “0” at the same time, a phenomenon known as superposition. (In traditional digital computing, transistors in silicon chips can exist in one of two states represented in binary by a 1 or 0 not both). Under the right conditions, computations carried out with qubits are equivalent to numerous classical computations performed in parallel, thus greatly enhancing computing power compared to today’s powerful supercomputers and the ability to solve complex problems without the sort of experiments necessary to generate quantum phenomena. this technology is unstable and needs to be stored in a cool environment for faster and more secure operation.In this paper, we discuss the possibility of integrating quantum computers with electronics at deep cryogenic temperatures.
Quantum computing promises an exponential speed-up of computation compared to what is nowadays achievable with classical computers. In this way, it enables the evaluation of more complex models and the breaching of current security algorithms. For the operation of a quantum system, many questions remain to be answered. Currently, there are several quantum technologies that promise to be both reliable and scalable, two features required for large scale quantum operations. Common to all technologies is the operating temperature that needs to be close to absolute zero, i.e. below 100 mK, to suppress environment noise and allow the quantum properties to become 'visible'. In order for any quantum processor to be operated, a so-called quantum-classical interface is required for the quantum bit (qubit) read-out and control. This interface consists of various electronic blocks, such as analog-to-digital converters, digital-to-analog converters, mixers, amplifiers and a digital controller. Especially the analog blocks require effort to meet the noise and stability constraints as not to disturb the very sensitive qubits and allow reading of the tiny signals. As the qubits live in extremely deep-cryogenic temperatures, long wires interface the cryogenic with the room temperature environment, where most of the electronics is situated. However, for a scalable system, heat injection becomes a serious problem, with many wires between 300 K and sub-Kelvin. Furthermore, such amount of interconnects is challenging to mechanically place in a dilution refrigerator. Therefore, in this work, we propose to implement the electronics not at room temperature, but at a temperature much closer to the qubits, for example at 4 K. This not only reduces significantly the wiring between room temperature and the qubits, but we can also benefit from lower electronic noise at such a temperature. The operation of conventional electronics almost 200°C below its normal temperature range is not trivial as device properties alter significantly and most circuits no longer operate as intended. In CMOS processes, the main technology in the integrated electronics world, the behaviour of the transistors, required for the implementation of any circuit, deviates considerably at low temperatures. The transistor's threshold voltage goes up, the mobility increases and the subthreshold slope becomes steeper, to name just a few of these deviations. Although there are improvements in performance, there are also some counter effects, and characterization of the transistors is needed to observe the changes. Once devices are characterized at such low temperatures, new models can be built and circuits can be simulated and adapted to operate properly at cryogenic temperatures. Luckily, there are various commercially available devices that can already withstand the chills of cold. We demonstrated various commercially available devices, such as a field-programmable gate array (FPGA) implemented in a 28 nm CMOS process, to be operating without major concerns at 4~K. Its properties alter only slightly, within 5 to 10%, and all tested circuit implementations, working at 300~K, also worked at 4 K. We combined both commercially available devices, that operate 200 K below their specified temperature range, with custom designed CMOS circuits to implement a cryogenic read-out platform for spin qubits. This system comprises amplifiers, an ADC, an FPGA, voltage regulators and a clock generator. It allows to amplify the tiny signal from the qubits and digitize it directly in the FPGA in order to process the data locally at 4~K. This system is one of the first systematic attempts at operating a part of the quantum-classical interface at cryogenic temperatures and forms the basis for future systems comprising the complete electronic interface for qubits to operate at such low temperatures. One of the main problems to tackle for cryogenic electronic systems is their power consumption. Power budgets are simply limited to roughly 1 or 2 Watts at 4 K and exponentially lower at deeper cryogenic temperatures, thus limiting the size of large-scale electronic systems. Our approach of combined commercial and custom circuits will have to be steadily replaced by a single (custom) technology that meets both power and scalability constraints. One of the best candidates is CMOS, a technology that the industry has relied upon for several decades and benefits from many optimizations thanks to Moore's law.
Quantum computing holds the promise to solve problems that are currently intractable by classical computing platforms. Such computing framework relies on the properties of quantum bits (qubits) that operates at cryogenic temperatures well below 1K. Besides a quantum processor, an operational quantum computer needs a classical electronic controller reading out the electrical signals generated by the qubits and the providing electrical control to perform the required operations on the qubits. Since today’s quantum processors comprise a low number of qubits (<10), most controlling electronics can operate at room temperature and be connected by bulky interconnects to the cryogenic qubit chamber. However, when scaling up to the thousands of qubits required in a practical quantum algorithm, the classical electronics must be placed at cryogenic temperature to simplify the interconnects and allow a compact, reliable and scalable system. In this work, we propose the fully-integrated implementation in standard CMOS technology of the electronic read-out for spin qubits. Simulations show that the proposed current read-out circuit can achieve a 10MHz bandwidth that is 10X wider than current state-of-the-art read-outs while keeping comparable noise performance and operating at 4.2K. Such results are a promising indication that cryogenic CMOS circuits can provide the building blocks for the integration of the classical electronic controller for future scalable quantum computers.
A fault tolerant scalable quantum computer requires more than 1000 Qubits to perform real time state correction and to improve the Qubit coherence time. The dense wiring connections required between the quantum processor placed at a 100 mK temperature and the room temperature control and readout electronics serve as a limiting factor in this system. Qubit control and readout electronics operating at 4 K temperature, placed closer to a quantum processor inside the dilution refrigerator avoids the dense wiring connections to room temperature electronics, and hence, serve as a potential solution to realize a scalable quantum computer. However, with no CMOS process technology models available at cryogenic temperatures, the design of a fully integrated, ultra-low power Qubit control and readout electronics at a sub-1 mW power consumption proves to be extremely challenging. In recent years, there has been a huge rise in interest among the research communities to understand and solve the device and circuit level challenges at deep cryogenic temperatures. This paper presents an overview of the recently published active and passive device nonidealities, circuit design challenges and solutions, and the future research directions in the Qubit control and readout electronics operating at deep cryogenic temperatures.
A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising a scalable solution to enable future quantum computers. In this paper, a cryogenic control system is proposed, along with the required specifications, for the interface of the classical electronics with the quantum processor. To prove the advantages of such a system, the functionality of key circuit blocks is experimentally demonstrated. The characteristic properties of cryo-CMOS are exploited to design a noise-canceling low-noise amplifier for spin-qubit RF-reflectometry readout and a class-F2,3digitally controlled oscillator required to manipulate the state of qubits.