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IEEE Computer Society Annual Symposium on VLSI

Area and Delay Efficient Design of a Quantum Bit String Comparator

Hafiz Md. Hasan Babu, Lafifa Jamal, Sayanton Vhaduri Dibbo, Ashis Kumer Biswas

Published Jul 1, 2017• 4 citations
Publisher

Abstract

This paper presents a new technique of magnitudecomparator for quantum bit string comparison. In the proposedmethod, the comparison between two quantum bit strings isperformed with the optimum number of operations. We have alsoshown that the proposed technique has time complexityO(( + )), whereas the best known existing technique hasO(nlog n),where n is the number of quantum bits. In addition, wehave proposed another technique to produce a compact quantumcomparator circuit. We have also introduced three new quantumgates with unique unitary matrices which represent the proposedquantum circuit more compactly than the existing quantumgates. The proposed comparator circuit has been designed usingthe proposed quantum bit comparator circuit named MidpointQubits Comparison (MQC) Circuit and another proposedquantum bit comparator circuit named Rest Qubits Comparison(RQC) Circuit. The comparative study shows that the proposedcomparator circuit outperforms the existing comparators; e.g.,the proposed 64-qubit comparator improves 7.19% on number ofquantum gates, area and delay; and 50.39% on garbage outputsover the existing best one

DOI
10.1109/isvlsi.2017.130

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This paper presents a new technique of magnitudecomparator for quantum bit string comparison. In the proposedmethod, the comparison between two quantum bit strings isperformed with the optimum number of operations. We have alsoshown that the proposed technique has time complexityO(( + )), whereas the best known existing technique hasO(nlog n),where n is the number of quantum bits. In addition, wehave proposed another technique to produce a compact quantumcomparator circuit. We have also introduced three new quantumgates with unique unitary matrices which represent the proposedquantum circuit more compactly than the existing quantumgates. The proposed comparator circuit has been designed usingthe proposed quantum bit comparator circuit named MidpointQubits Comparison (MQC) Circuit and another proposedquantum bit comparator circuit named Rest Qubits Comparison(RQC) Circuit. The comparative study shows that the proposedcomparator circuit outperforms the existing comparators; e.g.,the proposed 64-qubit comparator improves 7.19% on number ofquantum gates, area and delay; and 50.39% on garbage outputsover the existing best one
Quantum Bit String Comparators (QBSC) operate on two sequences of n-qubits, enabling the determination of their relationships, such as equality, greater than, or less than. This is analogous to the way conditional statements are used in programming languages. Consequently, QBSCs play a crucial role in various algorithms that can be executed or adapted for quantum computers. The development of efficient and generalized comparators for any nnn-qubit length has long posed a challenge, as they have a high-cost footprint and lead to quantum delays. Comparators that are efficient are associated with inputs of fixed length. As a result, comparators without a generalized circuit cannot be employed at a higher level, though they are well-suited for problems with limited size requirements. In this paper, we introduce a generalized design for the comparison of two nnn-qubit logic states using just two ancillary bits. The design is examined on the basis of qubit requirements, ancillary bit usage, quantum cost, quantum delay, gate operations, and circuit complexity, and is tested comprehensively on various input lengths. The work allows for sufficient flexibility in the design of quantum algorithms, which can accelerate quantum algorithm development.
This paper presents the design of a novel n-bit carry skip adder by its core components using quantum logic. The novelty of the proposed adder is that it considers a new design with optimal delay. Moreover, it is the first time in quantum circuit synthesis that the quantum realization of a carry skip adder is shown in terms of quantum gates, power and area, etc. Our proposed quantum multiplexer gate (QMG) and quantum comparison gate (QCG) perfectly operates as a 2-to-1 MUX and a comparison circuit, respectively. Using QMG and QCG as a unit element of construction, we optimize the design of Carry Skip Adder. A generalized architecture of the proposed n-bit adder has also been presented. The comparative study shows that the proposed quantum carry skip adder performs better than the existing carry skip adders with the increasing number of bits; e.g., the proposed 128-bit carry skip adder improves 40.96% on number of quantum gates, 48.19% on delay, 22.22% on garbage outputs and 40.96% on area and power over the existing best one. In addition, we also simulate the proposed adder using Microwind DSCH 3.5 and QuIDDPro software to show the correctness of the circuit.
This paper presents a new technique for designing a compact and an efficient quantum divider circuit. A backtracking technique has been incorporated to reduce the depth of the proposed design. In addition, we propose a new quantum full-subtractor circuit and a quantum ANDing circuit to perform the AND operation of the quantum bits. The proposed quantum divider circuit requires a linear depth, whereas the depth of the design of the best known existing quantum divider circuit is exponential. The comparative study shows that the proposed quantum divider improves 67.51% in terms of quantum gates, area, power and 53.33% in terms of constant inputs and 36.36% in terms of garbage outputs over the best known existing quantum divider when the dividend is a 64-qubit.
Reversible logic; transforms logic signal in a way that allows the original input signals to be recovered from the produced outputs, has attracted great attention because of its application in diverse areas such as quantum computing, low power computing, nanotechnology, DNA computing, quantum dot cellular automata, optical computing. In this paper, we design low power binary comparators using reversible logic gates. Firstly, single bit binary reversible comparator circuits are designed using different reversible gates along with proposed gate named Newly Proposed Gate. Then, these procedures are generalized for constructing binary n-bit reversible comparator circuit. The design synthesis consists of two parts: Comparator Cell and Propagator Cell. An algorithm, based on our proposed design, shows that proposed circuit reduces overall cost and it outperforms than existing sequential comparator circuits. Also, comparing with existing tree-based comparator circuit, proposed design reduces quantum cost, garbage output and gate count in a significance level which means better improvement as cost of any quantum circuit is directly associated with quantum cost, garbage output and gate count.
Quantum computing is at the leading edge of advanced technology that uses quantum phenomena such as entanglement and super position to solve complex problems. One of the main application is to built comparator circuit to do arithmetic operations at stipulated time. Based on this our research is to propose the design and implementation of one-bit and two-bit quantum comparators using IBM Qiskit, which is formly compared with classical comparator. Also this work represents a comprehensive overview of the techniques required to optimize and design quantum comparator circuits using real quantum simulators. The results obtained from simulation promises the comparison accuracy with classical results. From the circuit designed it is inferred that the hardware complexity is very much reduced compared to classical comparator, which are tabulated in terms of number of quantum gates. The proposed method can further be extended to generate higher order comparator circuits. These results may form the basis for further research and development that will support the advancement of quantum computing and algorithms.