aqora

Implementation of the Fully Asynchronous SFQ Microprocessor SCRAM2

Yusuke Nobumori, Kazunori Nakamiya, T. Nishigai +1 more

電子情報通信学会技術研究報告. SCE, 超伝導エレクトロニクスJun 29, 20060 citations

Demonstration of an SFQ/CMOS hybrid memory system using a one-instruction-set SFQ microprocessor

Yuki Hironaka, Yuki Yamanashi, Yoshikawa Nobuyuki

IEICE Technical Report; IEICE Tech. Rep.Apr 12, 20190 citations

Design and evaluation of data-path for low-power single-flux-quantum microprocessors

Yuhi Hayakawa, Takata Kensuke, Tanaka Masamitsu +1 more

IEICE Technical Report; IEICE Tech. Rep.Jul 15, 20130 citations

Quantum Microprocessor Architectures: Scalability and Error Correction Benchmark

Gabriel Silva Atencio

Lecture notes in civil engineeringJan 1, 20260 citations

10kA/cm^2プロセスを用いた2-bitビットスライス・アダーの設計と評価

賢介高田, 雄飛早川, 雅光田中 +1 more

A large number of researches on designing digital circuits by using SFQ logic circuits have been undertaken extensively. We have been developing SFQ microprocessors. In our demonstrated SFQ microprocessors, bit serial architectures were used. In order to increase the performance of the microprocessors, we have designed a bit-slice adder toward introduction of a bit-slice architecture. In this paper, we present a bit-parallel, serial, and slice architectures, and we compare and evaluate the operating times and circuit sizes of the adders based on these architectures. We also report design of a 2-bit bit-slice adder using AIST 10 kA/cm^2 niobium advanced process, and demonstration of its high-speed operation.A large number of researches on designing digital circuits by using SFQ logic circuits have been undertaken extensively. We have been developing SFQ microprocessors. In our demonstrated SFQ microprocessors, bit serial architectures were used. In order to increase the performance of the microprocessors, we have designed a bit-slice adder toward introduction of a bit-slice architecture. In this paper, we present a bit-parallel, serial, and slice architectures, and we compare and evaluate the operating times and circuit sizes of the adders based on these architectures. We also report design of a 2-bit bit-slice adder using AIST 10 kA/cm^2 niobium advanced process, and demonstration of its high-speed operation.

IEICE Technical Report; IEICE Tech. Rep.Jul 15, 20130 citations

Demonstration of a Single-Flux-Quantum Microprocessor Operating With Josephson-CMOS Hybrid Memory

Yuki Hironaka, Yuki Yamanashi, Nobuyuki Yoshikawa

We have been developing Josephson-CMOS hybrid memory to realize large-scale single-flux-quantum (SFQ) digital systems. In this article, we present the first demonstration of a Josephson-cryo complementary-metal-oxide-semicoductor (CMOS) memory hybrid system composed of an SFQ microprocessor and cryo-CMOS memory. We designed a single-instruction SFQ microprocessor whose data memory is implemented using Josephson-CMOS hybrid memory with a 16 × 4-b accessible address space. The Josephson and CMOS circuits were fabricated using the AIST Nb standard process and the Rohm 180-nm process, respectively. Low-frequency tests confirmed the correct operation of the single instruction SUBNEG (subtract and branch if negative), which verifies the read and write operations of data between the SFQ microprocessor and the hybrid memory. We also demonstrate the operation of an integer sorting program, which is composed of 16 SUBNEG instructions.We have been developing Josephson-CMOS hybrid memory to realize large-scale single-flux-quantum (SFQ) digital systems. In this article, we present the first demonstration of a Josephson-cryo complementary-metal-oxide-semicoductor (CMOS) memory hybrid system composed of an SFQ microprocessor and cryo-CMOS memory. We designed a single-instruction SFQ microprocessor whose data memory is implemented using Josephson-CMOS hybrid memory with a 16 × 4-b accessible address space. The Josephson and CMOS circuits were fabricated using the AIST Nb standard process and the Rohm 180-nm process, respectively. Low-frequency tests confirmed the correct operation of the single instruction SUBNEG (subtract and branch if negative), which verifies the read and write operations of data between the SFQ microprocessor and the hybrid memory. We also demonstrate the operation of an integer sorting program, which is composed of 16 SUBNEG instructions.

IEEE Transactions on Applied SuperconductivityMay 12, 202033 citations

C-8-12 Demonstration of SFQ Microprocessor data path to the Tornado Architecture

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