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IEEE International Symposium on Information Theory (ISIT)

On Decoding Error Performance of Binary Quantum Code with Mixed Letter States

Shogo Usami, Tsuyoshi Sasaki Usuda, Ichi Takumi, Masayasu Hata

Published Dec 4, 2001• 0 citations
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This letter considers an iterative decoding algorithm for non-binary linear block codes in which erasure and error decoding is performed for input words given by the sums of a hard-decision received sequence and given test patterns. We have proposed a new selection method of test patterns for the iterative decoding algorithm. Simulation results have shown that the decoding algorithm with test patterns by the proposed selection method provides better error performance than a conventional iterative decoding algorithm with the same number of the error and erasure decoding iterations over an additive white Gaussian noise channel using binary phase-shift keying modulation.

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Trapping sets of low-density parity-check codes are the problematic substructures that contribute to the error floor behavior under iterative decoding. Adoption of mixed scheduling for belief propagation decoding has shown to be very effective in solving some of the trapping sets. In this letter, we propose an adaptive mixed scheduling scheme that provides significantly improved code performance compared to existing mixed scheduling schemes.

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This letter considers an iterative decoding algorithm for non-binary linear block codes in which erasure and error decoding is performed for input words given by the sums of a hard-decision received sequence and given test patterns. We have proposed a new selection method of test patterns for the iterative decoding algorithm. Simulation results have shown that the decoding algorithm with test patterns by the proposed selection method provides better error performance than a conventional iterative decoding algorithm with the same number of the error and erasure decoding iterations over an additive white Gaussian noise channel using binary phase-shift keying modulation.
This letter proposes two methods to improve the iterative hard-reliability based majority-logic decoding algorithm for non-binary low-density parity-check (NB-LDPC) codes. The first method improves the error-correcting performance by modifying the initialization process, which is based on the fact that Gray coded modulation is used in general. In addition, a storage reduction method is proposed to make the proposed decoding hardware-friendly, which reduces the memory size considerably while sustaining the error-correcting performance achieved by the modified initialization. For an NB-LDPC code over Galois field of 32 elements, the memory size is reduced by about 75% compared with that of the conventional decoding algorithm.