This letter proposes two methods to improve the iterative hard-reliability based majority-logic decoding algorithm for non-binary low-density parity-check (NB-LDPC) codes. The first method improves the error-correcting performance by modifying the initialization process, which is based on the fact that Gray coded modulation is used in general. In addition, a storage reduction method is proposed to make the proposed decoding hardware-friendly, which reduces the memory size considerably while sustaining the error-correcting performance achieved by the modified initialization. For an NB-LDPC code over Galois field of 32 elements, the memory size is reduced by about 75% compared with that of the conventional decoding algorithm.
This letter proposes two methods to improve the iterative hard-reliability based majority-logic decoding algorithm for non-binary low-density parity-check (NB-LDPC) codes. The first method improves the error-correcting performance by modifying the initialization process, which is based on the fact that Gray coded modulation is used in general. In addition, a storage reduction method is proposed to make the proposed decoding hardware-friendly, which reduces the memory size considerably while sustaining the error-correcting performance achieved by the modified initialization. For an NB-LDPC code over Galois field of 32 elements, the memory size is reduced by about 75% compared with that of the conventional decoding algorithm.
Non-binary low-density parity-check (LDPC) codes have some advantages over their binary counterparts, but unfortunately their decoding complexity is a significant challenge. The iterative hard- and soft-reliability based majority-logic decoding algorithms are attractive for nonbinary LDPC codes, since they involve only finite field additions and multiplications as well as integer operations and, hence, have significantly lower complexity than other algorithms. In this paper, we propose two improvements to the majority-logic decoding algorithms. Instead of the accumulation of reliability information in the existing majority-logic decoding algorithms, our first improvement is a new reliability information update. The new update not only results in better error performance and fewer iterations on average, but also further reduces computational complexity. Since existing majority-logic decoding algorithms tend to have a high error floor for codes whose parity check matrices have low column weights, our second improvement is a reselection scheme, which leads to much lower error floors, at the expense of more finite field operations and integer operations, by identifying periodic points, reselecting intermediate hard decisions, and changing reliability information.
In the information theory , the non- binary low density parity check (NB-LDPC) code is a linear error correcting code , a method of transmitting message over a noisy transmission channel. LDPCcodes are capacity-approaching codes , which means that practical constructions exist that allow the noise threshold to be set very close to the theoretical maximum for a symmetric memory less channel.Using iterative belief propagation techniques, NB-LDPC codes can be decoded in time linear to their block length. Non-binary low-density parity-check codes can achieve higher performance than their binary counterparts. Recently, two algorithms were developed for decoding NB-LDPC codes: iterative hard reliability-based majority-logic decoding (IHRB-MLGD) and iterative soft reliability-based majority-logic decoding (ISRB-MLGD has better performance-complexity tradeoffs than previous algorithms. This paper first proposes message-passing in such a way that we can reduce the memory consumption to a greater extent at the same time there should not be performance loss. By using enhanced iterative reliability-based majority-logic decoding algorithms we can achieve effective complexity-performance and noise free design. Compared to previous designs, our proposed decoders have at least tens of times lower complexity with moderate coding gain loss.
In the nonbinary low-density parity check (NB-LDPC) codes decoding algorithms, the iterative hard reliability based on majority logic decoding (IHRB-MLGD) algorithm has poor error correction performance. The essential reason is that the hard information is used in the initialization and iterative processes. For the problem of partial loss of information, when the reliability is assigned during initialization, the error correction performance is improved by modifying the assignment of reliability at initialization. The initialization process is determined by the probability of occurrence of the number of erroneous bits in the symbol and the Hamming distance. In addition, the IHRB-MLGD decoding algorithm uses the hard decision in the iterative decoding process. The improved algorithm adds soft decision information in the iterative process, which improves the error correction performance while only slightly increasing the decoding complexity, and improves the reliability accumulation process which makes the algorithm more stable. The simulation results indicate that the proposed algorithm has a better decoding performance than IHRB algorithm.
Non-binary low-density parity-check (LDPC) codes have some advantages as opposed to their binary counterparts, but unfortunately their decoding complexity is a significant challenge. Hence, the iterative soft-reliability-based (ISRB) majority-logic decoding algorithm is attractive for non-binary LDPC codes, since it involves only finite field additions and multiplications as well as integer additions and comparisons. In this paper, we propose an improved ISRB majority-logic decoding algorithm by using a new reliability update. Our improved algorithm achieves better error performance and faster convergence, while further reducing the computational complexity. For instance, for a (16, 16)-regular (255, 175) cyclic Euclidean geometry LDPC code over GF(28), the proposed algorithm achieves a 0.15 dB coding gain and improves the convergence speed by 10% at a block error rate of 10-4versus the ISRB majority-logic decoding algorithm. Compared with the ISRB majority-logic decoding algorithm, the proposed algorithm requires the same numbers of finite field additions and multiplications but fewer integer additions and comparisons. Furthermore, the ISRB majority-logic decoding algorithm is based on the accumulation of reliability information, and hence the numerical range of the reliability information increases with iterations. In contrast, the proposed reliability update has a fixed numerical range and thus simplifies hardware implementations.
Non-binary low-density parity-check (NB-LDPC) codes have better error-correcting performance than their binary counterparts at the cost of higher decoding complexity when the code length is moderate. Compared to other NB-LDPC decoding algorithms, the iterative reliability-based majority-logic decoding can achieve better performance-complexity tradeoff. In this paper, an efficient partial-parallel shift-message decoder architecture is proposed for cyclic NB-LDPC codes based on the iterative soft reliability-based majority-logic decoding (ISRB-MLGD) algorithm. The message shifting is implemented by memories concatenated with variable node units to reduce the area. Although the accumulated soft reliabilities in the ISRB algorithm require longer word length, and accordingly longer critical path and larger memory, the decoder architecture and control logic can be simplified. Particularly, the check node units are modified so that the message switching network can be eliminated. Compared to the iterative hard reliability-based decoder for a (255, 175) NB-LDPC code over GF(28), the proposed ISRB decoder can achieve around 0.8dB coding gain with less than three times hardware complexity.
Non-binary low-density parity-check (NB-LDPC) codes usually exhibit much better performance than their binary counterparts. Among NB-LDPC decoding algorithms, the iterative reliability-based majority-logic decoding (MLGD) algorithms are attractive for their low computation complexity, at the cost of performance degradation. In this brief, based on the improved iterative soft reliability-based (IISRB)-MLGD algorithm, we propose a clipped-modified (CM)-IISRB algorithm, which achieves better decoding performance with lower computational complexity. First, two modifications are introduced to the IISRB algorithm, which considerably reduces the decoding complexity with negligible performance loss. Second, an unsaturated-clipping method that facilitates significant performance improvement is presented. Simulation results show that the new algorithm outperforms the IISRB by about 0.2dB for the 256-ary (255, 175) example code. Moreover, based on a new storage reduction method, an optimized architecture is developed for the CM-IISRB algorithm. Synthesis results demonstrate that the proposed decoder can achieve very low hardware complexity, comparable to that of the iterative hard reliability-based (IHRB) decoder.