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IEEE Transactions on Circuits & Systems II Express Briefs

A Novel Iterative Reliability-Based Majority-Logic Decoder for NB-LDPC Codes

Suwen Song, Hangxuan Cui, Jing Tian, Jun Ting Lin, Zhongfeng Wang

Published Aug 30, 2019• 7 citations
Publisher

Abstract

Non-binary low-density parity-check (NB-LDPC) codes usually exhibit much better performance than their binary counterparts. Among NB-LDPC decoding algorithms, the iterative reliability-based majority-logic decoding (MLGD) algorithms are attractive for their low computation complexity, at the cost of performance degradation. In this brief, based on the improved iterative soft reliability-based (IISRB)-MLGD algorithm, we propose a clipped-modified (CM)-IISRB algorithm, which achieves better decoding performance with lower computational complexity. First, two modifications are introduced to the IISRB algorithm, which considerably reduces the decoding complexity with negligible performance loss. Second, an unsaturated-clipping method that facilitates significant performance improvement is presented. Simulation results show that the new algorithm outperforms the IISRB by about 0.2dB for the 256-ary (255, 175) example code. Moreover, based on a new storage reduction method, an optimized architecture is developed for the CM-IISRB algorithm. Synthesis results demonstrate that the proposed decoder can achieve very low hardware complexity, comparable to that of the iterative hard reliability-based (IHRB) decoder.

DOI
10.1109/tcsii.2019.2938562

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•Aug 31, 2014•0 citations
Non-binary low-density parity-check (NB-LDPC) codes usually exhibit much better performance than their binary counterparts. Among NB-LDPC decoding algorithms, the iterative reliability-based majority-logic decoding (MLGD) algorithms are attractive for their low computation complexity, at the cost of performance degradation. In this brief, based on the improved iterative soft reliability-based (IISRB)-MLGD algorithm, we propose a clipped-modified (CM)-IISRB algorithm, which achieves better decoding performance with lower computational complexity. First, two modifications are introduced to the IISRB algorithm, which considerably reduces the decoding complexity with negligible performance loss. Second, an unsaturated-clipping method that facilitates significant performance improvement is presented. Simulation results show that the new algorithm outperforms the IISRB by about 0.2dB for the 256-ary (255, 175) example code. Moreover, based on a new storage reduction method, an optimized architecture is developed for the CM-IISRB algorithm. Synthesis results demonstrate that the proposed decoder can achieve very low hardware complexity, comparable to that of the iterative hard reliability-based (IHRB) decoder.
Non-binary low-density parity-check (NB-LDPC) codes tend to exhibit much better performance than their binary counterparts while suffering from very high computational complexity. As a type of hard-decision NB-LDPC decoding algorithm, the iterative reliability-based majority-logic decoding (IRB-MLGD) algorithms are attractive for their low computation complexity, coming with obvious performance degradation. Aiming at improving the error-correction performance, in this paper, we introduce few redundant bits to the original NB-LDPC encoding and the corresponding checksum operations to the improved iterative soft reliability-based (IISRB)-MLGD. Based on the joint coding and decoding method, the obtained redundancy-aided (RA)-IISRB decoding algorithm shows significant performance improvement while maintaining the low-complexity property. Simulation results demonstrate that the proposed algorithm can achieve a more than 1.0dB extra coding gain over the original IISRB with a slight decrease of code rate.
When non-binary low-density parity-check (NB-LDPC) codes with low column weights are adopted, the iterative reliability-based majority-logic decoding (IRB-MLGD) algorithms suffer from severe performance degradation compared to message passing algorithms. In this brief, based on the improved iterative soft reliability-based (IISRB)-MLGD algorithm, we propose a perturbation-injected (P)-IISRB algorithm, where a regular perturbation is introduced to alleviate the periodic point problem that is the main reason for IISRB decoding failure. Compared with the conventional IISRB, the new algorithm significantly improves the decoding performance, lowering the error-floor by at least two orders of magnitude for the example code. Besides, instead of traditionally pre-computing and storing all the q-ary channel reliability measures, a real-time computing method is presented, which reduces the memory cost fromO( q) toO( log2q).
Non-binary low-density parity-check (NB-LDPC) codes have some advantages as opposed to their binary counterparts, but unfortunately their decoding complexity is a significant challenge. Hence, iterative hard-reliability-based majority-logic decoding (IHRB-MLGD) algorithms are attractive for NB-LDPC codes due to their low complexities. In this paper, we propose a layered improved iterative hard-reliability-based majority-logic decoding algorithm and design a partly parallel architecture for the proposed algorithm. Our improved algorithm achieves better error performance and faster convergence than existing IHRB-MLGD algorithms, while maintaining low complexities. The proposed partly parallel architecture achieves a throughput of 779 Mbps with SMIC 0.13um CMOS technology.
Non-binary low-density parity-check (NB-LDPC) codes have better error-correcting performance than their binary counterparts at the cost of higher decoding complexity when the code length is moderate. Compared to other NB-LDPC decoding algorithms, the iterative reliability-based majority-logic decoding can achieve better performance-complexity tradeoff. In this paper, an efficient partial-parallel shift-message decoder architecture is proposed for cyclic NB-LDPC codes based on the iterative soft reliability-based majority-logic decoding (ISRB-MLGD) algorithm. The message shifting is implemented by memories concatenated with variable node units to reduce the area. Although the accumulated soft reliabilities in the ISRB algorithm require longer word length, and accordingly longer critical path and larger memory, the decoder architecture and control logic can be simplified. Particularly, the check node units are modified so that the message switching network can be eliminated. Compared to the iterative hard reliability-based decoder for a (255, 175) NB-LDPC code over GF(28), the proposed ISRB decoder can achieve around 0.8dB coding gain with less than three times hardware complexity.
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than their binary counterparts at the cost of higher decoding complexity when the codeword length is moderate. The recently developed iterative reliability-based majority-logic NB-LDPC decoding has better performance complexity tradeoffs than previous algorithms. This paper first proposes enhancement schemes to the iterative hard reliability-based majority-logic decoding (IHRB-MLGD). Compared to the IHRB algorithm, our enhanced (E)-IHRB algorithm can achieve significant coding gain with small hardware overhead. Then low-complexity partial-parallel NB-LDPC decoder architectures are developed based on these two algorithms. Moreover, novel schemes are developed to keep a small proportion of messages in order to reduce the memory requirement without causing noticeable performance loss. In addition, a shift-message structure is proposed by using memories concatenated with variable node units to enable efficient partial-parallel decoding for cyclic NB-LDPC codes. our proposed decoders have at least tens of times lower complexity with moderate coding gain loss.
In the information theory , the non- binary low density parity check  (NB-LDPC) code is a  linear error correcting code , a method of transmitting message over a  noisy transmission channel. LDPCcodes are  capacity-approaching codes , which  means  that  practical constructions exist  that allow the noise threshold to be set very close to the theoretical maximum for a symmetric memory less channel.Using iterative  belief propagation techniques, NB-LDPC codes can be decoded in time linear to their block length. Non-binary low-density parity-check codes can achieve higher performance than their binary counterparts. Recently, two algorithms were developed for decoding NB-LDPC codes: iterative hard reliability-based majority-logic decoding (IHRB-MLGD) and iterative soft reliability-based majority-logic decoding (ISRB-MLGD has better performance-complexity tradeoffs than previous algorithms. This paper first proposes message-passing in such a way that we can reduce the memory consumption to a greater extent at the same time there should not be performance loss. By using enhanced iterative reliability-based majority-logic decoding algorithms we can achieve effective complexity-performance and noise free design. Compared to previous designs, our proposed decoders have at least tens of times lower complexity with moderate coding gain loss.