IEEE International Symposium on Circuits and Systems proceedings

Low-complexity layered iterative hard-reliability-based majority-logic decoder for non-binary quasi-cyclic LDPC codes

Chenrong Xiong, Zhiyuan Yan

Published May 1, 2013• 5 citations

Abstract

Non-binary low-density parity-check (NB-LDPC) codes have some advantages as opposed to their binary counterparts, but unfortunately their decoding complexity is a significant challenge. Hence, iterative hard-reliability-based majority-logic decoding (IHRB-MLGD) algorithms are attractive for NB-LDPC codes due to their low complexities. In this paper, we propose a layered improved iterative hard-reliability-based majority-logic decoding algorithm and design a partly parallel architecture for the proposed algorithm. Our improved algorithm achieves better error performance and faster convergence than existing IHRB-MLGD algorithms, while maintaining low complexities. The proposed partly parallel architecture achieves a throughput of 779 Mbps with SMIC 0.13um CMOS technology.

DOI: 10.1109/iscas.2013.6572104

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