A garbage output is an output that is needed to change an irreversible gate to a reversible one and are not used to the input to the other gates. 2.3 Quantum cost All reversible 1 × 1 and 2 × 2 gates have unity quantum cost. As every reversible gate is a combination of 1 × 1 or 2 × 2 quantum gate, so the quantum cost of a reversible gate is the numbers of quantum gate (Thapliyal et al. 2010).
A garbage output is an output that is needed to change an irreversible gate to a reversible one and are not used to the input to the other gates. 2.3 Quantum cost All reversible 1 × 1 and 2 × 2 gates have unity quantum cost. As every reversible gate is a combination of 1 × 1 or 2 × 2 quantum gate, so the quantum cost of a reversible gate is the numbers of quantum gate (Thapliyal et al. 2010).
Background/Objectives: The objective is to reduce the Quantum Cost (QC), Garbage Output (GO) and Gate Counts in the design of the adder by incorporating the Novel Reversible Gates. Methods/Statistical Analysis: In recent day’s energy dissipation is the major complex problem in circuit designing in order to recede this problem the reversible logic is employed, where the input vectors can be derived from the output vectors and from the output vectors the input vectors can be procured. Using this technique the Quantum Cost, Garbage Outputs and Gate Counts of the design is reduced. Findings: Based on the technique of reversible logic a novel reversible Gates is proposed from that the novel reversible adders have been designed. The novel reversible gates satisfy the property of reversibility and universality which shows the uniqueness of the proposed gates. The comparative analysis have been made with the existing work, the proposed work shows a significant improvement in the design optimization parameters. Application/Improvements: The proposed structures can be employed in the ALU design and in Floating Point Multiplier design. The comparative analysis shows that Number of Gates, Garbage Outputs and Quantum Cost is minimum for the proposed gate based structure rather than conventional one Keywords: Garbage Outputs (GO), QCA, Quantum Cost (QC), Reversibility, Reversible Logic, Universality.
In this paper the authors have proposed a new 3×3 reversible gate and also proposed the reversible combinational logic circuits with better optimized quantum cost, garbage outputs and delay.The proposed new reversible logic gate is used to design of reversible 1-bit comparator circuit and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR.The proposed new reversible logic gate is represented by quantum implementation.The quantum cost of proposed gate is 4. The quantum cost, garbage output and delay of proposed reversible 1-bit comparator circuit are 6 which is better w. r. t. previously reported results.
This paper presents the quantum cost (QC), garbage output (GO) and constant input (CI) optimized 2:4 decoder using reversible logic gate. The proposed reversible circuit is design using existing reversible logic gate, such as reversible NOT gate, Feynman gate and Peres gate. The proposed decoder can be design using one Peres gate, one NOT gate and four Feynman gate. The QC, GO and CI of the proposed 2:4 decoder is 9, 0 and 2. Which is better w.r.t previously reported work. This is the first reversible 2:4 decoder circuit, which has `0' garbage output. The improvement % of QC, GO and CI are 0 - 74.28 %, 100 % and 33.33 - 75 %.
Aim and Objective: This paper presents the quantum cost, garbage output, constant input and number of reversible gate optimized 2:4 decoder using 4×4 new reversible logic gate which is named as reversible decoder block or RD block. Method: The proposed block is implemented with a quantum circuit and quantum cost of the proposed RD block is 8. The proposed decoder can be designed using only one new proposed block. Results and Conclusion: The quantum cost, garbage output, constant input and gate number of the proposed 2:4 decoder is 9, 0, 2 and 1 which is better w.r.t previously reported work. The improvement % of quantum cost, garbage output, constant input and number of gates are 12.5 – 77.148 %, 100 %, 33.33 – 75 % and 0 – 85.71%.
In recent years, reversible logic circuits have applications in the emerging field of digital signal processing, optical information processing, quantum computing and nano technology. Reversibility plays an important role when computations with minimal energy dissipation are considered. The main purpose of designing reversible logic is to decrease the number of reversible gates, garbage outputs, constant inputs, quantum cost, area, power, delay and hardware complexity of the reversible circuits. This paper reveals a comparative review on various reversible logic gates. This paper provides some reversible logic gates, which can be used in designing more complex systems having reversible circuits and can execute more complicated operations using quantum computers. Future digital technology will use reversible logic gates in order to reduce the power consumption and propagation delay as it effectively provides negligible loss of information in the circuit. Keywords: Garbage output, Power dissipation, quantum cost, Reversible Gate, Reversible logic,
Reversible logic is expanding grounds with its applicability to various upcoming technologies and quantum computation. Numerous reversible gates has also been proposed for designing logic circuits apart of basic quantum controlled Toffoli and Fredkin gates. A comparative study and analysis of a range of reversible gates from the literature is presented in this paper to obtain an optimal solution for designing these circuits. The gates are synthesized and implemented to obtain equivalent quantum circuits and operating cost in terms of number of inputs, gate cost, quantum cost, garbage output and ancilla input. The comparison is done at two subsequent levels i.e. gates structural level and circuit design level, providing a better solution for designing logic circuits. It is calculated that, basic gates are 50% efficient at gate level and 33% at design level analysis in terms of gate cost, as compared to the most efficient gates proposed in the literature.