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IEEE Transactions on Applied Superconductivity

Reduction of the supply current of single-flux-quantum time-to-digital converters by current recycling techniques

Kyosuke Sano, Tomoki Shimoda, Yutaka Abe, Yuki Yamanashi, Nobuyuki Yoshikawa, Nobuyuki Zen, M. Ohkubo

Published Dec 30, 2016• 20 citations
Publisher

Abstract

We have been developing superconducting time-of-flight mass spectrometry systems that utilize superconducting strip particle detectors and single-flux-quantum (SFQ) time-to-digital converters (TDCs). We previously demonstrated a 24-bit SFQ TDC with a 3 × 24-bit first-in first-out (FIFO) buffer using the AIST Nb standard process (STP2) with a time resolution of 100 ps. In this study, we improved the SFQ TDC by using a current recycling technique. The technique enables us to increase the FIFO buffer capacity without increasing the total supply current, and the result is an improvement of ion count rates. We designed and demonstrated the SFQ TDC with a 12 × 24-bit FIFO buffer, whose total supply current was reduced by 71% with the current recycling technique.

DOI
10.1109/tasc.2016.2646916

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We have been developing superconducting time-of-flight mass spectrometry systems that utilize superconducting strip particle detectors and single-flux-quantum (SFQ) time-to-digital converters (TDCs). We previously demonstrated a 24-bit SFQ TDC with a 3 × 24-bit first-in first-out (FIFO) buffer using the AIST Nb standard process (STP2) with a time resolution of 100 ps. In this study, we improved the SFQ TDC by using a current recycling technique. The technique enables us to increase the FIFO buffer capacity without increasing the total supply current, and the result is an improvement of ion count rates. We designed and demonstrated the SFQ TDC with a 12 × 24-bit FIFO buffer, whose total supply current was reduced by 71% with the current recycling technique.
We have been developing a superconducting time-of-flight mass spectrometry (TOF-MS) system, which utilizes a superconductive strip ion detector (SSID) and a single-flux-quantum (SFQ) multi-stop time-to-digital converter (TDC). The SFQ multi-stop TDC can measure the time intervals between multiple input signals and directly convert them into binary data. In this study, we designed and implemented 24-bit SFQ multi-stop TDCs with a 3×24-bit FIFO buffer using the AIST Nb standard process (STP2), whose time resolution and dynamic range are 100ps and 1.6ms, respectively. The timing jitter of the TDC was investigated by comparing two types of TDCs: one uses an on-chip SFQ clock generator (CG) and the other uses a microwave oscillator at room temperature. We confirmed the correct operation of both TDCs and evaluated their timing jitter. The experimentally-obtained timing jitter is about 40ns and 700ps for the TDCs with and without the on-chip SFQ CG, respectively, for the measured time interval of 50µs, which linearly increases with increase of the measured time interval.
We have been developing a time-to-digital converter (TDC) using single-flux-quantum (SFQ) circuits in order to realize an imaging system based on a superconducting strip single-photon detector (SSPD). In this system, the absorption position of a single photon in a meander-shaped SSPD is determined by measuring the delay time of the detected signal propagating through an SSPD delay line. Increasing the time resolution of the TDC is the primary concern for improving the spatial resolution of the system. Here we focused on the double-oscillator SFQ TDC, where the difference of oscillation periods between two SFQ ring oscillators determines the time resolution. In the previous study, a time resolution of about 4 ps was demonstrated by using the Nb standard Josephson integrated circuit (IC) process with a critical current density of 2.5 kA/cm2. In this study, we improved the time resolution by adopting the Nb advanced Josephson IC process with a critical current density of 10 kA/cm2and by optimizing the circuit parameters of the coincidence detector. The histogram and the linearity of the delay measurements show that the time resolution is improved to up to 2 ps.
We have designed, fabricated, and successfully tested a Time-to-Digital converter (TDC). The TDC circuit consists of superconductive counters based on toggle flip-flops with destructive readout, shift registers, parallel-to-serial converters, and pulse detectors. The value of the counter is latched while the counter is operating at full speed. The TDC resolution is directly determined by the maximum counter speed, or 50 ps for an available 20 GHz clock rate. The circuits are implemented in HYPRES' standard Nb process with a critical current density of 1.0 kA/cm/sup 2/ using HYPRES' library of standard RSFQ cells.
As single flux quantum (SFQ) circuit complexities scale, larger bias currents are required. The large current produces excessive heat and greatly complicates the design process. Current recycling offers a solution by reducing the required bias current through serially biased circuit blocks. Serial biasing is typically achieved in homogeneous SFQ systems where similar bias currents are required in similar circuits. Each of these homogeneous circuits is often placed on different ground planes and serially biased to reuse the bias currents. To address heterogeneous circuits with varying bias current requirements, a novel serial biasing technique is proposed. An interface between the ground planes with unequal bias current is presented that exhibits a current balancing capability. The interface supplies additional current before passing the current to the next ground plane. The ground planes are arranged in ascending order of bias current to manage the complexity of these heterogeneous circuits. Using a one bit SFQ full adder as an example, the proposed approach demonstrates several key benefits: a 49% reduction in the number of driver-receiver pairs, a 6.5% reduction in power dissipation, and a 35% reduction in bias current across a heterogeneous SFQ circuit placed on three isolated ground planes. The performance, bias current margins, and methods for current reduction are also discussed, showcasing the effectiveness of current recycling in improving the efficiency of complex heterogeneous SFQ systems.
Superconducting nanowire single-photon detectors (SNSPDs) with series-parallel meander-type configurations are demonstrated to have photon-number-resolving capabilities and are expected to be used for an evaluation system of single-photon generators and/or an energy-resolved fast detector for a new-generation time-of-flight mass spectrometry. In this paper, we present the design, fabrication, and confirmation of correct operations of two kinds of single-flux-quantum (SFQ) digital readout circuits for an SNSPD with a series-parallel meander-type configuration. Assuming a six-parallel meander-type configuration, we designed: a six-level current discriminator using six different magnetically coupled DC/SFQ converter circuits; and a Δ-type A/D converter using a quasi-one-junction SQUID (QOS) comparator with an SFQ feedback loop. For the design of the magnetically coupled inputs, we used a 3-D inductance extraction program FastHenry and the designed circuits were fabricated using a HYPRES 4.5-kA/cm2Nb process and a National Institute of Advanced Industrial Science and Technology (AIST) standard 2.5-kA/cm2Nb process.
Abstract One of the unique applications of single-flux-quantum (SFQ) circuitry is a digital-to-analog converter (DAC) of which the output voltage is defined by the Josephson effect. Recently, we have designed and operated rapid single-flux-quantum (RSFQ) DACs with frequency modulation of SFQ pulse sequences. In this paper, we report our design and test results of a 4-bit RSFQ-DAC based on the configuration of the “sum of selected bits sequence (Σ-SBS)”. By adjusting the timing margins, in addition to the fabrication using the Nb integration process with the critical current density as high as 10 kA/cm2, the maximum output voltage up to 260 μV was demonstrated.