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SiPS ... design and implementation - IEEE Workshop on Signal Processing Systems

Stochastic BP Polar Decoding and Architecture with Efficient Re-Randomization and Directive Register

Menghui Xu, Xiao Liang, Chuan Zhang, Zhizhen Wu, Xiaohu You

Published Oct 1, 2016• 14 citations
Publisher

Abstract

Recently, polar codes have gained their popularity because of its capacity achieving property. On the other hand, representing continuous values by unary bit streams, stochastic decoding shows its advantages in both hardware efficiency and error resilience. Therefore, this paper devotes itself in combining both together to offer a stochastic belief propagation (BP) polar decoder, which is suitable for applications requiring low complexity, high fault tolerance, but not sensitive to processing speed. In this paper, several approaches such as bit length increasing and efficient re-randomization are proposed and carefully analyzed to improve the decoding performance. Numerical results have shown that for N = 64 and N = 256, the proposed stochastic BP decoder can achieve comparable decoding performance as the deterministic one. Hardware architecture employing directive register is also proposed in detail for efficient implementation of the proposed stochastic decoder.

DOI
10.1109/sips.2016.62

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Recently, polar codes have gained their popularity because of its capacity achieving property. On the other hand, representing continuous values by unary bit streams, stochastic decoding shows its advantages in both hardware efficiency and error resilience. Therefore, this paper devotes itself in combining both together to offer a stochastic belief propagation (BP) polar decoder, which is suitable for applications requiring low complexity, high fault tolerance, but not sensitive to processing speed. In this paper, several approaches such as bit length increasing and efficient re-randomization are proposed and carefully analyzed to improve the decoding performance. Numerical results have shown that for N = 64 and N = 256, the proposed stochastic BP decoder can achieve comparable decoding performance as the deterministic one. Hardware architecture employing directive register is also proposed in detail for efficient implementation of the proposed stochastic decoder.
Polar codes, being the first class of codes with provable capacity-achieving property, have aroused extensive attention. The belief propagation (BP) algorithm, which is one of the popular decoding approaches for polar codes, possesses inherent high parallelism but also high computational complexity. With low complexity and high fault tolerance, stochastic computing has been well studied and applied to BP decoding for polar codes. However, existing stochastic BP decoders suffer from high decoding latency. In this paper, firstly, a novel dual-bit-wise iterative message update method is proposed for stochastic BP, reducing the decoding latency by more than half. Based on the dual-bit-wise decoding, more special nodes in the factor graph are investigated and then fully exploited to pursue lower decoding complexity than prior arts. Moreover, a well-optimized architecture is developed for the proposed stochastic decoder, where the random number generator (RNG), tracking forecast memory (TFM), and hard decision unit are intelligently designed for reduced hardware cost. Experimental results demonstrate that the presented decoder can exhibit 61.7% lower decoding latency than the state-of-the-art works. Besides, the throughput and hardware efficiency can be improved by nearly2.8×2.8\times2.8×and2.7×2.7\times2.7×, respectively.
Polar codes have received recent attention due to their potential to be applied in advanced wireless communication protocols such as the fifth generation mobile communication system (5G). Among the existing decoding algorithms, Belief Propagation (BP) exhibits high-throughput, low-latency, and soft output with a high hardware cost. Stochastic computing, as a form of approximate computing, provides a potential low-cost implementation solution for the BP algorithm. However, existing stochastic BP decoders suffer from a relatively long decoding latency resulting in low hardware efficiency. In this paper, a novel bit-wise iterative stochastic decoding architecture for the BP algorithm is proposed to improve the throughput and hardware efficiency. By utilizing the frozen bits of polar codes and stochastic computing, multiple novel optimization methods are presented to further speed up convergence and increase the hardware efficiency.
Polar codes have received recent attention due to their potential to be applied in advanced wireless communication protocols such as the fifth generation mobile communication system (5G). Among the existing decoding algorithms, Belief Propagation (BP) exhibits high-throughput, low-latency and soft output with a high hardware cost. A form of approximate computing called stochastic computing provides a low-cost implementation solution for the BP algorithm. However, existing stochastic BP decoders suffer from a relatively long decoding latency resulting in low hardware efficiency. In this paper, a novel bit-wise iterative stochastic decoding architecture for the BP algorithm is proposed to improve the throughput and hardware efficiency. Multiple methods at the algorithm and architecture levels are presented to further speed up convergence and hardware efficiency.
Representing continuous values by streams of random binary bits, stochastic decoding has shown advantages in both hardware efficiency and fault tolerance, therefore has been widely adopted by iterative decoding of error correction codes such as low-density parity-check (LDPC) codes and so on. Recently, polar codes, the first codes that can provably achieve the capacity of symmetric binary-input discrete memoryless channels (B-DMCs), have drawn a lot of attentions from both academia and industry. Although, polar codes with list successive cancellation (SC) decoding can outperform several best-known LDPC codes even within high error-rate regions, the linearly increasing hardware complexity makes its efficient implementation difficult. To this end, the stochastic list SC polar decoding algorithm is proposed in this paper to provide a good tradeoff between performance and complexity. In order to increase the decoding performance of stochastic list SC polar decoder, doubling probability approach is presented. The corresponding hardware architecture is also given. The approximate doubling approach is employed to facilitate the efficient implementation. Implementation results have shown that the proposed stochastic list SC polar decoder can achieve a good trade-off between performance and complexity.
Belief propagation (BP) decoding of polar codes benefits from the high parallelism in hardware implementation and consequently provides high throughput compared to successive cancellation-based decoding algorithms. As the evolved log-likelihood ratios (LLRs) in the decoding process have a wide dynamic range, the quantization error can degrade the error correction performance of the BP decoder. To reduce the quantization error in a uniform quantization scheme, we may need to use more bits for each LLR value which is not desirable due to the required memory space. In this paper, we design an efficient hardware architecture for non-uniformly quantized LLR messages in BP decoding where the arithmetic operations on logarithmically compressed messages are replaced with the mapping to precomputed results in lookup tables. By employing 5-bit non-uniform quantization, the designed BP decoder architecture reduces the required memory space by 37.5 percent compared to 8-bit uniform quantization while additionally improving the block error rate (BLER) by more than 0.1 dB in high SNR regimes. Compared to uniform quantization, the BLER improvement of the designed architecture is up to 0.4 dB when both quantization schemes use 5 bits for LLRs.
Polar codes have emerged as the most favorable channel codes for their unique capacity-achieving property. To date, numerous approaches for efficient decoding of polar codes have been reported. However, these prior efforts focused on design of polar decoders via deterministic computation, while the behavior of stochastic polar decoder, which can have potential advantages such as low complexity and strong error-resilience, has not been studied in existing literatures. This paper, for the first time, investigates polar decoding using stochastic logic. Specifically, the commonly-used successive cancellation (SC) algorithm is reformulated into the stochastic form. Several methods that can potentially improve decoding performance are discussed and analyzed. Simulation results show that a stochastic SC decoder can achieve similar error-correcting performance as its deterministic counterpart. This work can pave the way for future hardware design of stochastic polar codes decoders.