Today the error correcting codes are present in all the telecom standards, in particular the low density parity check (LDPC) codes. The choice of a good code for a given network is essentially linked to the decoding performance obtained by the bit error rate (BER) curves. This approach requires a significant simulation time proportional to the length of the code, to overcome this problem Exit chart was introduced, as a fast technique to predict the performance of a particular class of codes called Turbo codes. In this paper, we success to apply Exit chart to analyze convergence behavior of iterative threshold decoding of one step majority logic decodable (OSMLD) codes. The iterative decoding process uses a soft-input soft-output threshold decoding algorithm as component decoder. Simulation results for iterative decoding of simple and concatenated codes transmitted over a Gaussian channel have shown that the thresholds obtained are a good indicator of the Bit Error Rate (BER) curves.
Today the error correcting codes are present in all the telecom standards, in particular the low density parity check (LDPC) codes. The choice of a good code for a given network is essentially linked to the decoding performance obtained by the bit error rate (BER) curves. This approach requires a significant simulation time proportional to the length of the code, to overcome this problem Exit chart was introduced, as a fast technique to predict the performance of a particular class of codes called Turbo codes. In this paper, we success to apply Exit chart to analyze convergence behavior of iterative threshold decoding of one step majority logic decodable (OSMLD) codes. The iterative decoding process uses a soft-input soft-output threshold decoding algorithm as component decoder. Simulation results for iterative decoding of simple and concatenated codes transmitted over a Gaussian channel have shown that the thresholds obtained are a good indicator of the Bit Error Rate (BER) curves.
In this paper, we devise a non-binary version of the Soft-Input Soft-Output Iterative Threshold Decoder (ITD). This is a continuation of our work where the devised algorithm is the upgrade of the non-iterative non-binary Soft-Input Hard-Output Threshold Decoder (TD), which is itself an upgrade of previous work on the Hard-Input Hard-Output non-binary Majority-Logic Decoder (MLGD). The proposed ITD showed an improvement compared to its predecessors where coding gains of 1.5dB and 2.5dB were observed compared to the TD algorithm and the MLGD algorithm respectively, at a bit error rate (BER) of 10-5. The proposed decoder is best suited for One-Step Majority-Logic decodable codes with a large orthogonal structure in their dual codes, such as finite geometry codes, which are also Low-Density Parity-Check codes. The performances of our decoder are presented in terms of bit, symbol, and block error rates, and the proposed decoder has shown to outperform the best well-known decoders for LDPC codes as displayed by the simulation results. Where the proposed decoder offers a coding gain of 1dB compared to the Min-Max algorithm, 1.5dB of coding gain compared to the ISRB algorithm, and 1.6dB of coding gain compared to the KV algorithm at a block error rate (BLER) of 10-4. Also, the computational complexity of our decoder is proven to be lower than that of the ISRB algorithm, which has itself been proven to be less complex than the other algorithms in the study conducted by its authors.
In modern communication systems Low-Density Parity Check (LDPC) codes are widely used. It is because of their performance under iterative decoding, hardware-friendly structure and well-known construction methods. For one to construct good LDPC code Density Evolution (DE) can be used, it estimates the decoding threshold, that is it estimates performance of the code. LDPC codes can be further extended to Generalized LDPC (GLDPC) codes, where simple SPC code is replaced with some component code. With more complex structure common DE is no longer correct. This letter presents the upper bound for decoding error and, therefore, an upper bound of a iterative threshold (in dB). It will be shown that the Gaussian approximation gives an upper bound for a decoding error. As one of the results it means that EXIT-charts analysis also gives an upper bound for an iterative threshold for a GLDPC code.
Low density parity check (LDPC) codes are known to achieve a performance very close to the Shannon capacity limit on Additive White Gaussian Noise (AWGN) and erasure channels. The extrinsic information transfer (EXIT) chart is a powerful method for analyzing iteratively decoded codes such as Turbo codes. EXIT charts were introduced as a method for representing how the mutual information between the decoder output and the transmitted bits changes over turbo decoding iterations. It is possible to apply the EXIT chart method to LDPC codes by treating the LDPC decoder as a concatenation of variable and check nodes. However the achieved convergence threshold values obtained with the EXIT charts are (plusmn0.1) dB away from the more precise results derived from the density evolution (DE) method. Subsequently, the EXIT trajectories method was proposed as an improved performance-analysis method for LDPC codes under belief propagation (BP) decoding and achieved more accurate convergence threshold values than the EXIT chart method. In this paper, the EXIT chart and the EXIT trajectories methods are proposed as analysis tools to compare between the BP, log likelihood and max log likelihood decoding algorithms for LDPC codes in terms of convergence thresholds. Furthermore, a comparison between EXIT chart, EXIT trajectories and DE methods is introduced for the mentioned LDPC codes. Simulations and numerical calculations on convergence thresholds for various ensembles of (dv, dc) regular LDPC codes for binary input AWGN channels are performed which results that the BP is the best decoding algorithm for LDPC code followed by the log likelihood and the max log likelihood algorithms, respectively. Also, the EXIT trajectory method yields more accurate results than EXIT charts which come very close to the DE method, while being more convenient numerically as a code research tool than the latter which require many Fourier transform operations.
After the introduction of iterative coding, Low Density Parity Check (LDPC) codes have received a lot of attention due to their remarkable near Shannon-limit performance and practical decoder implementation. However, when employing an LDPC code for various applications, multiple issues do arise at the simulation, algorithm and implementation levels. The first issue is the performance evaluation of the iterative LDPC decoder in the very low Bit Error Rate (BER) regions. So far, no analytical tool has been developed to evaluate the performance of LDPC codes. Unfortunately standard Monte Carlo (MC) simulations cannot be used for performance estimation in these low BER regions due to prohibitive execution times. The second issue is the efficiency of the decoding algorithm. Due to the presence of short cycles in the bipartite graph, sum-product decoding algorithms lead to considerable performance loss for short block-length LDPC codes and produce error floors for longer codes. In addition, the iterative processing and estimation of soft probabilistic values with these algorithms result in very high computational complexity, which in turn impedes the adoption of LDPC codes for power constrained systems. Another prime objective is to design a high throughput decoder architecture which is capable of supporting multiple rates and variable code lengths within minimal area.
This work aims to address and provide solutions to the above problems. As a solution to the performance estimation problem of LDPC codes, a highly efficient and novel fast BER simulation technique is developed. At the algorithm level, a performance improvement and error floor avoidance method is introduced, and a computationally efficient algorithm is developed for the sum-product decoding of LDPC codes. And finally, at the architecture level, a high throughput multi-rate variable code length implementation is presented which, when implemented, efficiently minimizes device resources while alleviating the routing complexity of the decoder.
The bit-error-rate (BER) performance of 3-dimensional (3D) product codes under iterative bounded-distance decoding of the component codes is considered and a framework for analyzing the BER-performance is presented. The performance analysis of iterative decoding is based on a graphical model of the underlying 3D product code, which is a tripartite 3-uniform hypergraph. The BER performance for 3D product codes shows a threshold behavior. The thresholds can be approximated by an exit-chart-like technique from the parameters of the component codes. In the case of a symmetric product code, for which all three component codes are based on the same lineart-error correcting code, asymptotically for large code lengths, the BER-threshold is determined by the threshold for the appearance of ak-core withk=t+ 1 in the graphical model.
Low-density parity-check (LDPC) codes have received significant attention due to their near-Shannon-limit error performance. The belief propagation (BP) algorithm is the best-known decoding algorithm for LDPC codes. However it often needs several tens or hundreds of iterations to converge. Although fast convergence BP algorithms have been proposed, there is neither an easy tool to analyze their performance nor a standard VLSI architecture to implement them. Moreover, there exists a trade-off between waterfall (i.e., threshold) and error floor (i.e., minimum pseudo distance) performances for LDPC codes. For generalized LDPC (GLDPC) codes, better minimum distance properties can be achieved but at the expense of a rate loss. This research investigates performance analysis and hardware implementation of LDPC codes using fast convergence algorithms. Closed-form extrinsic mutual information transfer (EXIT) functions for several fast convergence BP decoding algorithms are proposed. It is shown theoretically that these algorithms converge faster than standard BP, while the corresponding thresholds remain unchanged. Since these algorithms are of serial nature, their parallelization without compromising convergence speed and error performance is also investigated. This result is useful in hardware implementation because in practice partly parallel decoding schemes are often used. This result also sheds some light on how to group nodes in order to preserve performance. The VLSI architecture of a particular decoding algorithm for LDPC codes is proposed. This approach can be adopted in many standards to achieve a large throughput. Doubly GLDPC (DGLDPC) codes are proposed to compensate the rate loss of GLDPC codes. EXIT charts are used to analyze DGLDPC codes and EXIT functions for variable component codes are thoroughly discussed. Based on EXIT charts, differential evolution is used to optimize their threshold. Ensemble weight enumerators are generalized to protograph-based DGLDPC codes. Simulation results show that DGLDPC codes constructed based on these results can improve the performance of their LDPC and GLDPC counterparts in both the waterfall region and the error floor region.