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International Conference on Advanced Communication Technologies and Networking (CommNet)

A New Iterative Threshold Decoding Algorithm for non-binary OSMLD Codes

Zakaria M’rabet, Fouad Ayoub, Mostafa Belkasmi

Published Dec 12, 2022• 0 citations
Publisher

Abstract

In this paper, we devise a non-binary version of the Soft-Input Soft-Output Iterative Threshold Decoder (ITD). This is a continuation of our work where the devised algorithm is the upgrade of the non-iterative non-binary Soft-Input Hard-Output Threshold Decoder (TD), which is itself an upgrade of previous work on the Hard-Input Hard-Output non-binary Majority-Logic Decoder (MLGD). The proposed ITD showed an improvement compared to its predecessors where coding gains of 1.5dB and 2.5dB were observed compared to the TD algorithm and the MLGD algorithm respectively, at a bit error rate (BER) of 10-5. The proposed decoder is best suited for One-Step Majority-Logic decodable codes with a large orthogonal structure in their dual codes, such as finite geometry codes, which are also Low-Density Parity-Check codes. The performances of our decoder are presented in terms of bit, symbol, and block error rates, and the proposed decoder has shown to outperform the best well-known decoders for LDPC codes as displayed by the simulation results. Where the proposed decoder offers a coding gain of 1dB compared to the Min-Max algorithm, 1.5dB of coding gain compared to the ISRB algorithm, and 1.6dB of coding gain compared to the KV algorithm at a block error rate (BLER) of 10-4. Also, the computational complexity of our decoder is proven to be lower than that of the ISRB algorithm, which has itself been proven to be less complex than the other algorithms in the study conducted by its authors.

DOI
10.1109/commnet56067.2022.9993922

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In this paper, we devise a non-binary version of the Soft-Input Soft-Output Iterative Threshold Decoder (ITD). This is a continuation of our work where the devised algorithm is the upgrade of the non-iterative non-binary Soft-Input Hard-Output Threshold Decoder (TD), which is itself an upgrade of previous work on the Hard-Input Hard-Output non-binary Majority-Logic Decoder (MLGD). The proposed ITD showed an improvement compared to its predecessors where coding gains of 1.5dB and 2.5dB were observed compared to the TD algorithm and the MLGD algorithm respectively, at a bit error rate (BER) of 10-5. The proposed decoder is best suited for One-Step Majority-Logic decodable codes with a large orthogonal structure in their dual codes, such as finite geometry codes, which are also Low-Density Parity-Check codes. The performances of our decoder are presented in terms of bit, symbol, and block error rates, and the proposed decoder has shown to outperform the best well-known decoders for LDPC codes as displayed by the simulation results. Where the proposed decoder offers a coding gain of 1dB compared to the Min-Max algorithm, 1.5dB of coding gain compared to the ISRB algorithm, and 1.6dB of coding gain compared to the KV algorithm at a block error rate (BLER) of 10-4. Also, the computational complexity of our decoder is proven to be lower than that of the ISRB algorithm, which has itself been proven to be less complex than the other algorithms in the study conducted by its authors.
Non-binary low-density parity-check (LDPC) codes have some advantages as opposed to their binary counterparts, but unfortunately their decoding complexity is a significant challenge. Hence, the iterative soft-reliability-based (ISRB) majority-logic decoding algorithm is attractive for non-binary LDPC codes, since it involves only finite field additions and multiplications as well as integer additions and comparisons. In this paper, we propose an improved ISRB majority-logic decoding algorithm by using a new reliability update. Our improved algorithm achieves better error performance and faster convergence, while further reducing the computational complexity. For instance, for a (16, 16)-regular (255, 175) cyclic Euclidean geometry LDPC code over GF(28), the proposed algorithm achieves a 0.15 dB coding gain and improves the convergence speed by 10% at a block error rate of 10-4versus the ISRB majority-logic decoding algorithm. Compared with the ISRB majority-logic decoding algorithm, the proposed algorithm requires the same numbers of finite field additions and multiplications but fewer integer additions and comparisons. Furthermore, the ISRB majority-logic decoding algorithm is based on the accumulation of reliability information, and hence the numerical range of the reliability information increases with iterations. In contrast, the proposed reliability update has a fixed numerical range and thus simplifies hardware implementations.
In the information theory , the non- binary low density parity check  (NB-LDPC) code is a  linear error correcting code , a method of transmitting message over a  noisy transmission channel. LDPCcodes are  capacity-approaching codes , which  means  that  practical constructions exist  that allow the noise threshold to be set very close to the theoretical maximum for a symmetric memory less channel.Using iterative  belief propagation techniques, NB-LDPC codes can be decoded in time linear to their block length. Non-binary low-density parity-check codes can achieve higher performance than their binary counterparts. Recently, two algorithms were developed for decoding NB-LDPC codes: iterative hard reliability-based majority-logic decoding (IHRB-MLGD) and iterative soft reliability-based majority-logic decoding (ISRB-MLGD has better performance-complexity tradeoffs than previous algorithms. This paper first proposes message-passing in such a way that we can reduce the memory consumption to a greater extent at the same time there should not be performance loss. By using enhanced iterative reliability-based majority-logic decoding algorithms we can achieve effective complexity-performance and noise free design. Compared to previous designs, our proposed decoders have at least tens of times lower complexity with moderate coding gain loss.
Non-binary low-density parity-check (NB-LDPC) codes have better error-correcting performance than their binary counterparts at the cost of higher decoding complexity when the code length is moderate. Compared to other NB-LDPC decoding algorithms, the iterative reliability-based majority-logic decoding can achieve better performance-complexity tradeoff. In this paper, an efficient partial-parallel shift-message decoder architecture is proposed for cyclic NB-LDPC codes based on the iterative soft reliability-based majority-logic decoding (ISRB-MLGD) algorithm. The message shifting is implemented by memories concatenated with variable node units to reduce the area. Although the accumulated soft reliabilities in the ISRB algorithm require longer word length, and accordingly longer critical path and larger memory, the decoder architecture and control logic can be simplified. Particularly, the check node units are modified so that the message switching network can be eliminated. Compared to the iterative hard reliability-based decoder for a (255, 175) NB-LDPC code over GF(28), the proposed ISRB decoder can achieve around 0.8dB coding gain with less than three times hardware complexity.
Today the error correcting codes are present in all the telecom standards, in particular the low density parity check (LDPC) codes. The choice of a good code for a given network is essentially linked to the decoding performance obtained by the bit error rate (BER) curves. This approach requires a significant simulation time proportional to the length of the code, to overcome this problem Exit chart was introduced, as a fast technique to predict the performance of a particular class of codes called Turbo codes. In this paper, we success to apply Exit chart to analyze convergence behavior of iterative threshold decoding of one step majority logic decodable (OSMLD) codes. The iterative decoding process uses a soft-input soft-output threshold decoding algorithm as component decoder. Simulation results for iterative decoding of simple and concatenated codes transmitted over a Gaussian channel have shown that the thresholds obtained are a good indicator of the Bit Error Rate (BER) curves.
This paper presents a majority-logic based message-passing algorithm for decoding non-binary LDPC codes. Recently, many majority-logic decoding (MLGD) algorithms make huge efforts on reducing the computational complexity for decoding non-binary LDPC codes. Inspired by one step majority-logic decoding and q-ary sum-product algorithm, we devise a novel iterative double-reliability-based (IDRB) MLGD algorithm which carries out an efficient trade-off between decoding computational complexity and error performance. The proposed algorithm achieves a remarkable enhancement on error correct ability and yet requires only integer operations and finite field operations. Simulation results on two NB-LDPC codes show that we succeed in achieving significant coding gain compared with IHRB- and ISRB-MLGD with limited complexity increase.
Non-binary low-density parity-check (LDPC) codes have some advantages over their binary counterparts, but unfortunately their decoding complexity is a significant challenge. The iterative hard- and soft-reliability based majority-logic decoding algorithms are attractive for nonbinary LDPC codes, since they involve only finite field additions and multiplications as well as integer operations and, hence, have significantly lower complexity than other algorithms. In this paper, we propose two improvements to the majority-logic decoding algorithms. Instead of the accumulation of reliability information in the existing majority-logic decoding algorithms, our first improvement is a new reliability information update. The new update not only results in better error performance and fewer iterations on average, but also further reduces computational complexity. Since existing majority-logic decoding algorithms tend to have a high error floor for codes whose parity check matrices have low column weights, our second improvement is a reselection scheme, which leads to much lower error floors, at the expense of more finite field operations and integer operations, by identifying periodic points, reselecting intermediate hard decisions, and changing reliability information.