Low-temperature superconducting circuits have become important for many scientific applications. However, there are presently no high current-capacity switches (~1 mA) with low power dissipation for sub-Kelvin operation. One candidate for a sub-Kelvin switch is the cryotron, a device in which the superconductivity of a wire is suppressed with a magnetic field. Here, we demonstrate a cryotron switch suitable for sub-Kelvin temperatures. In the closed state, the maximum device current is about 900 μA. The device is switched to its open state with 2 mA of control current and has a leakage of approximately 500 nA. The transition between the closed and open states of the device is faster than 200 ns, where the measurement is limited by the speed of our measurement apparatus. We also discuss low-temperature applications for our cryotron such as a single-pole, double-throw switch.
Low-temperature superconducting circuits have become important for many scientific applications. However, there are presently no high current-capacity switches (~1 mA) with low power dissipation for sub-Kelvin operation. One candidate for a sub-Kelvin switch is the cryotron, a device in which the superconductivity of a wire is suppressed with a magnetic field. Here, we demonstrate a cryotron switch suitable for sub-Kelvin temperatures. In the closed state, the maximum device current is about 900 μA. The device is switched to its open state with 2 mA of control current and has a leakage of approximately 500 nA. The transition between the closed and open states of the device is faster than 200 ns, where the measurement is limited by the speed of our measurement apparatus. We also discuss low-temperature applications for our cryotron such as a single-pole, double-throw switch.
Scalable superconducting nanowire single photon detector (SNSPDs) arrays require cryogenic digital circuits for multiplexing the output detection pulses. Among existing superconducting digital devices, superconducting nanowire cryotron (nTron) is a three-terminal device with an ultra-compact size, which is promising for large scale monolithic integration. In this report, in order to evaluate the potential and possibility of using nTrons for reading and digitizing SNSPD signals, we characterized the grey zone, speed, timing jitter and power dissipation of a proper designed nTron. With a DC bias on the gate, the nTron can be triggered by a few μA high and nanoseconds wide input signal, showing the nTron was capable of reading an SNSPD pulse at the same signal level. The timing jitter depended on the input signal level. For a 20 μA high and 5 ns wide input pulse, the timing jitter was 33.3 ps, while a typical SNSPD's jitter was around 50 ps. With removing the serial inductors and operating it in an AC bias mode. The nTron was demonstrated to be operated at a clock frequency of 615.4 MHz, which was faster than the maximum counting rate of a typical SNSPD. In additional, with a 50 Ω bias resistor and biased at 17.6 μA, the nTron had a total power dissipation of 19.7 nW. Although RSFQ circuits are faster than nTrons, for reading SNSPD or other detector arrays that demands less operation speed, our results suggest a digital circuit made from nTrons could be another promising alternative.
Superconducting (SC) electronics (SCE) is one of the major requirements to develop a large-scale practical quantum computing system. (Figs. 1(a)) [1]. Currently, a room temperature conventional computer is used as the control processor which requires a huge number of lossy interconnects to connect with the qubits placed at a few millikelvin temperatures. This, in turn, limits the scalability of the quantum computing system up to hundreds of qubits which is not enough to achieve the full potential [2]. Therefore, along with a suitable cryogenic memory, a cryogenic (preferably superconducting) control processor is required to develop a quantum computing system with thousands of qubits. Moreover, SCE offers ultra-fast (hundreds of gigahertz) and highly energy efficient (sub attojoule/bit) performance [3]. Therefore, SCE is projected to achieve the department of energy (DOE) exascale goal which the conventional supercomputers failed to achieve (Fig. 1(b)) [4]. However, Josephson junction-based SC circuits suffer from limited integration density due to flux trapping, difficulty in driving large impedances, fanning out digital signals, and operating in noisy environments [5]. To address these existing issues, here, we present a novel reconfigurable SC logic circuit using a nano-cryotron (nTron) that can perform 1-input copy, 2-input AND and OR, and 3-input majority logic functionalities. This work can enable the implementation of highly scalable and energy-efficient SC processor since the use of only one device. To achieve the reconfigurable nature of the logic circuit, we utilize the multi-gate switching of nTron.
Abstract Many classic and quantum devices need to operate at cryogenic temperatures, demanding advanced cryogenic digital electronics for processing the input and output signals on a chip to extend their scalability and performance. Here, we report a superconducting binary encoder with ultralow power dissipation and ultracompact size. We introduce a multigate superconducting nanowire cryotron (nTron) that functions as an 8-input OR gate within a footprint of approximately 0.5 μm2. Four cryotrons compose a 4-bit encoder that has a bias margin of 18.9%, an operation speed greater than 250 MHz, an average switching jitter of 75 ps, and a power dissipation of less than 1 μW. We apply this encoder to read out a superconducting-nanowire single-photon detector array whose pixel location is digitized into a 4-bit binary address. The small size of the nanowire combined with the low power dissipation makes nTrons promising for future monolithic integration.
Cryogenic (cryo) memory devices, designed to operate at/below 4 Kelvin (K) temperature, is a prime enabler of practical quantum computing systems, and superconducting (SC) electronic platforms (Figs. 1(a), (b)) [1]. The state-of-the-art quantum algorithms require many arbitrary rotations which demand a large memory to store program instructions [2]. SC qubits (used in most of the existing quantum computing systems) are highly sensitive to noise and hence, to protect the qubit states from thermal disturbances, they are placed at a few milli-Kelvin (mK) temperature. Furthermore, to preserve the integrity of the quantum states, the SC qubits undergo continuous error correction schemes, requiring extensive memory and bandwidth [2]. Superconducting electronics (SCE) (targeted towards space applications, and high-performance computing) outperforms the conventional CMOS counterparts in terms of speed and energy-efficiency (Fig. 1(c)) [3]. Decades of research efforts have given rise to three major categories (and several sub-variants) of cryo-memories based on SC, non-SC, and hybrid technologies (Fig. 2) [2], [4]–[6]. However, the existing variants suffer from one or more of the following challenges - (i) limited scalability, (ii) process complexity, (iii) bulky peripherals, (iv) array-level interference, (v) volatility, and (vi) speed incompatibility. Therefore, a scalable cryo-memory system remains elusive. To address these existing issues, here, we present a novel cryo-memory system utilizing -(i) the polarization-induced Cooper-pair [7] modulation in a ferroelectric(FE)superconducting quantum interference device (SQUID) (Fig. 3(a)) [8], and (ii) current controlledSC↔non−SCswitching in a heater cryotron(hTron)(Fig. 4) [4]. Discrete prototypes of these devices have been demonstrated recently, but their coupled interactions (which we harness in our work) were never explored before.
We have constructed tunneling cryotron flip-flops, have observed current transfer from one leg to the other, and have measured the time required for current transfer to be 2 nsec. The results are in agreement with the model previously proposed.1 The tunneling cryotron flip-flop consists of two devices in parallel, linked by a wholly superconducting path. A current is fed to the parallel devices; the current is steered from one device to the other by application of a control pulse. The measurements have been made on a loop of 1.16 in. in length (L=1.08×10−10H), containing two 10 mil diam junctions, having zero-field critical currents of 21 mA and 29 mA, respectively (in operation these are biased to near maxima on the gain curves, at 33 mA and 42 mA). The measuring apparatus is similar to that previously described.1 In operation, a current of 20 mA is transferred from one device to the other by the application of a 2 mA control pulse, a gain of 10. The time required for this current to transfer, Δttransfer, is 1.4 nesc≤Δttransfer≤2.0 nsec, with an uncertainty of at most 0.4 nsec. According to the previously proposed model of a constant gap voltage driving the loop inductance and which does not include the junction transition times (Ref. 1), the transfer time for 20 mA of current should be 2 nsec. One implication of this excellent agreement is that the junction transition time is appreciably smaller than the previously measured upper bound of 800 psec.2 Additional operating details will be discussed.