In this paper, 3D architecture for TSV integrated Si surface ion-trap is proposed, in which the TSV and microbump technology is used to connect the surface electrodes of ion trap to a bottom Si interposer. The pseudopotential simulation is used to determine the trapped ion height for both the “planar trap” and “TSV trap” geometry. No significant deviation in the pseudopotential for both cases is observed. Preliminary micro-fabricated ion-trap chips are characterized. The proposed technology is promising in form factor and parasitic reduction of micro-fabricated surface ion-trap for scalable quantum computing application.
We present the design, fabrication, and characterization of a monolithic, segmented, three-dimensional linear Paul ion trap for quantum science applications. The trap is fabricated from a single fused-silica block using selective laser-induced etching (SLE) and is subsequently metallized, forming electrodes isolated by self-shadowing trench structures without the need for layer alignment or external shadow masks. The segmented electrodes allow for shaping of the axial potential, enabling the creation of anharmonic potential wells, such as those required for equidistant ion strings. In addition, they enable shuttling and splitting of ion chains. We discuss key design choices and SLE-imposed constraints on achievable feature sizes, and evaluate electron-beam evaporation and magnetron sputtering as metallization approaches. Across two independent experimental setups, we demonstrate stable trapping and control of linear chains of up to 33
40Ca
+ ions, including approximately equally spaced configurations. The measured secular frequencies in both traps agree with boundary-element simulations at the percent level, with residual deviations attributed to stray electric fields in the presence of anharmonic axial potentials, rather than fabrication imperfections. We measure axial micromotion field strengths on the order of 100 V/m along the trap axis, in approximate agreement with simulations. For radial mode frequencies near 2 MHz and an ion-electrode distance of 300 um, we measure heating rates of the order of 10 quanta/s in all but one motional mode, which is elevated by a technical noise source. The presented trap design is thus suitable for a wide range of quantum science applications and demonstrates the viability of SLE for the fabrication of finely segmented, monolithic, three-dimensional ion traps.
Ion trap is a promising approach to realizing scalable quantum computer as it presents high coherence time. Silicon, due to its manufacturability, is being considered as a potential substrate to fabricate complex ion-trap designs towards trap miniaturization and on-chip integration of electronics and optics. However, Si ion traps need proper structural design to reduce the substrate RF loss. In this paper, high-resistivity Si substrate materials has been utilized to fabricate surface electrode ion trap. Its DC and RF properties has been investigated and compared to the ion trap fabricated on sapphire substrate, which is one of the most established substrate material for trap fabrication.