Quantum circuit model

Jingwen Chen, Qun Liu, Yanhong Fan +3 more

In recent years, quantum technology has been rapidly developed. As security analyses for symmetric ciphers continue to emerge, many require an evaluation of the resources needed for the quantum circuit implementation of the encryption algorithm. In this regard, we propose the quantum circuit decision problem, which requires us to determine whether there exists a quantum circuit for a given permutation f using M ancilla qubits and no more than K quantum gates within the circuit depth D. Firstly, we investigate heuristic algorithms and classical SAT-based models in previous works, revealing their limitations in solving the problem. Hence, we innovatively propose an improved SAT-based model incorporating three metrics of quantum circuits. The model enables us to find the optimal quantum circuit of an arbitrary 3 or 4-bit S-box under a given optimization goal based on SAT solvers, which has proved the optimality of circuits constructed by the tool, LIGHTER-R. Then, by combining different criteria in the model, we find more compact quantum circuit implementations of S-boxes such as RECTANGLE and GIFT. For GIFT S-box, our model provides the optimal quantum circuit that only requires 8 gates with a depth of 31. Furthermore, our model can be generalized to linear layers and improve the previous SAT-based model proposed by Huang et al. in ASIACRYPT 2022 by adding the criteria on the number of qubits and the circuit depth.

Madhusudan Singh Irish Singh, Bharat S. Rawal

László Gyöngyösi

The power of quantum computers makes it possible to solve difficult problems more efficiently than is possible with traditional computers. Gate-model quantum computers provide an experimentally implementable architecture for quantum circuit computations. Here, we demonstrate an automated method for designing quantum circuits for experimental gate-model quantum computers. We define the Quantum Triple Annealing Minimization (QTAM) algorithm, which provides an automated quantum circuit minimization on the physical layout (circuit depth and area), quantum wire length minimization of the quantum circuit, Hamiltonian minimization, and the minimization of the input size and output measurements. We define a multilayer structure for quantum circuit computations using the hardware restrictions on the connection topology of gate-model quantum computers. The results can be straightforwardly applied to near term gate-model quantum computers.

Dipankar Bhattacharyya, Jyotirmoy Guha

Evan E. Dobbs, Robert Basmadjian, Alexandru Paler +1 more

Predicting the optimum SWAP depth of a quantum circuit is useful because it informs the compiler about the amount of necessary optimization. Fast prediction methods will prove essential to the compilation of practical quantum circuits. In this paper, we propose that quantum circuits can be modeled as queuing networks, enabling efficient extraction of the parallelism and duration of SWAP circuits. To provide preliminary substantiation of this approach, we compile a quantum multiplier circuit and use a queuing network model to accurately determine the quantum circuit parallelism and duration. Our method is scalable and has the potential speed and precision necessary for large scale quantum circuit compilation.