Predicting the optimum SWAP depth of a quantum circuit is useful because it informs the compiler about the amount of necessary optimization. Fast prediction methods will prove essential to the compilation of practical quantum circuits. In this paper, we propose that quantum circuits can be modeled as queuing networks, enabling efficient extraction of the parallelism and duration of SWAP circuits. To provide preliminary substantiation of this approach, we compile a quantum multiplier circuit and use a queuing network model to accurately determine the quantum circuit parallelism and duration. Our method is scalable and has the potential speed and precision necessary for large scale quantum circuit compilation.
Predicting the optimum SWAP depth of a quantum circuit is useful because it informs the compiler about the amount of necessary optimization. Fast prediction methods will prove essential to the compilation of practical quantum circuits. In this paper, we propose that quantum circuits can be modeled as queuing networks, enabling efficient extraction of the parallelism and duration of SWAP circuits. To provide preliminary substantiation of this approach, we compile a quantum multiplier circuit and use a queuing network model to accurately determine the quantum circuit parallelism and duration. Our method is scalable and has the potential speed and precision necessary for large scale quantum circuit compilation.
Abstract Quantum circuit compilation is an indispensable part of executing quantum circuits on quantum devices. It translates logical quantum circuits into physical quantum circuits that meet the device constraints. However, nonspecialist users require extensive expertise to effectively select and evaluate quantum circuit compilation processes. Therefore, this paper proposes a quantum circuit compilation option prediction method based on Deep Residual Attention Neural Network. The method aims to automate the selection of the best compilation scheme and enhance the efficiency and accuracy of quantum circuit compilation. Firstly, a quantum circuit feature extraction algorithm based on Time-Weighted Interaction Graph is proposed. This algorithm can effectively represent quantum circuits using fixed-length vectors, making the model input scalable. Secondly, for existing one-dimensional features, a quantum circuit compilation option prediction model based on Deep Residual Attention Neural Network is designed and trained. This model is capable of quickly and accurately predicting the optimal compilation option combination. Extensive experimental evaluations and comparisons are carried out on the MQT (Munich Quantum Toolkit) quantum circuit compilation dataset. These evaluations verify the effectiveness and advancement of the proposed method. Compared with the current state-of-the-art method (Random Forest), the proposed method improves the accuracy by 5.44%, the Top-3 accuracy by 2.6%, and the F1 by 2.05%.
Layout synthesis is mapping a quantum circuit to a quantum processor. SWAP gate insertions are needed for scheduling 2-qubit gates only on connected physical qubits. With the ever-increasing number of qubits in NISQ processors, scalable layout synthesis is of utmost importance. With large optimality gaps observed in heuristic approaches, scalable exact methods are needed. While recent exact and near-optimal approaches scale to moderate circuits, large deep circuits are still out of scope. In this work, we propose a SAT encoding based on parallel plans that apply 1 SWAP and a group of CNOTs at each time step. Using domain-specific information, we maintain optimality in parallel plans while scaling to large and deep circuits. From our results, we show the scalability of our approach which significantly outperforms leading exact and near-optimal approaches (up to 100x). For the first time, we can optimally map several 8, 14, and 16 qubit circuits onto 54, 80, and 127 qubit platforms with up to 17 SWAPs. While adding optimal SWAPs, we also report near-optimal depth in our mapped circuits.
Abstract Compiling quantum circuits is a major bottleneck in quantum computing, and given the scale required in a few years, is likely to become infeasibly long. Techniques to reduce compilation time for quantum circuits are sorely needed. Furthermore, resources to test acceleration techniques are similarly lacking due to the limited scale of circuits in benchmark suites and mismatches in characteristics of these circuits and those produced by random circuit generators. This paper resolves the latter of these problems by describing a random circuit generator which allows control of circuit density, width and depth parameters. This is used to derive 8000 experimental large-scale circuits and test a novel approach to compiler parallelisation. This separates a circuit into sub-circuits, which are compiled in parallel and recombined to produce a compiled circuit. When the parallel approach was tested using Qiskit, a peak speedup of 15.56 was achieved with corresponding overheads of less than 1%.
Compiling quantum circuits is a major bottleneck in quantum computing, and given the scale required in a few years, is likely to become infeasibly long. Techniques to reduce compilation time for quantum circuits are sorely needed. Furthermore, resources to test acceleration techniques are similarly lacking due to the limited scale of circuits in benchmark suites and mismatches in characteristics of these circuits and those produced by random circuit generators. This paper resolves the latter of these problems by describing a random circuit generator which allows control of circuit density, width and depth parameters. This is used to derive 8000 experimental large-scale circuits and test a novel approach to compiler parallelisation. This separates a circuit into sub-circuits which are compiled in parallel and recombined to produce a compiled circuit. When the parallel approach was tested using Qiskit, a peak speedup of 15.56 was achieved with corresponding overheads of less than 1%.
Abstract Quantum noise in real-world devices poses a significant challenge in achieving practical quantum advantage, since accurately compiled and executed circuits are typically deep and highly susceptible to decoherence. To facilitate the implementation of complex quantum algorithms on noisy hardware, we propose an approximate method for compiling target quantum circuits into brick-wall layouts. This new circuit design consists of two-qubit CNOT gates that can be directly implemented on real quantum computers, in conjunction with optimized one-qubit gates, to approximate the essential dynamics of the original circuit while significantly reducing its depth. Our approach is evaluated through numerical simulations of time-evolution circuits for the critical Ising model, quantum Fourier transformation, and Haar-random quantum circuits, as well as experiments on IBM quantum platforms. By accounting for compilation error and circuit noise, we demonstrate that time evolution and quantum Fourier transformation circuits achieve high compression rates, while random quantum circuits are less compressible. The degree of compression is related to the rate of entanglement accumulation in the target circuit. In particular, experiments on IBM platforms achieve a compression rate of 12.5 for N=12, significantly extending the application of current quantum devices. Furthermore, large-scale numerical simulations for system sizes up to N=30 reveal that the optimal depth dmax to achieve maximal overall fidelity is independent of system size N, suggesting the scalability of our method for large quantum devices in terms of quantum resources.
Abstract In this work we propose a high-quality decomposition approach for qubit routing by swap insertion. This optimization problem arises in the context of compiling quantum algorithms formulated in the circuit model of computation onto specific quantum hardware. Our approach decomposes the routing problem into an allocation subproblem and a set of token swapping problems. This allows us to tackle the allocation part and the token swapping part separately. Extracting the allocation part from the qubit routing model of Nannicini et al. (Optimal qubit assignment and routing via integer programming, 2021, http://arxiv.org/abs/2106.06446 ), we formulate the allocation subproblem as a binary linear program. Herein, we employ a cost function that is a lower bound on the overall routing problem objective. We strengthen the linear relaxation by novel valid inequalities. For the token swapping part we develop an exact branch-and-bound algorithm. In this context, we improve upon known lower bounds on the token swapping problem. Furthermore, we enhance an existing approximation algorithm which runs much faster than the exact approach and typically is able to determine solutions close to the optimum. We present numerical results for the fully integrated allocation and token swapping problem. Obtained solutions may not be globally optimal due to the decomposition and the usage of an approximation algorithm. However, the solutions are obtained fast and are typically close to optimal. In addition, there is a significant reduction in the number of artificial gates and output circuit depth when compared to various state-of-the-art heuristics. Reducing these figures is crucial for minimizing noise when running quantum algorithms on near-term hardware. As a consequence, using the novel decomposition approach leads to compiled algorithms with improved quality. Indeed, when compiled with the novel routing procedure and executed on real hardware, our experimental results for quantum approximate optimization algorithms show an significant increase in solution quality in comparison to standard routing methods.