Compiling quantum circuits is a major bottleneck in quantum computing, and given the scale required in a few years, is likely to become infeasibly long. Techniques to reduce compilation time for quantum circuits are sorely needed. Furthermore, resources to test acceleration techniques are similarly lacking due to the limited scale of circuits in benchmark suites and mismatches in characteristics of these circuits and those produced by random circuit generators. This paper resolves the latter of these problems by describing a random circuit generator which allows control of circuit density, width and depth parameters. This is used to derive 8000 experimental large-scale circuits and test a novel approach to compiler parallelisation. This separates a circuit into sub-circuits which are compiled in parallel and recombined to produce a compiled circuit. When the parallel approach was tested using Qiskit, a peak speedup of 15.56 was achieved with corresponding overheads of less than 1%.
Compiling quantum circuits is a major bottleneck in quantum computing, and given the scale required in a few years, is likely to become infeasibly long. Techniques to reduce compilation time for quantum circuits are sorely needed. Furthermore, resources to test acceleration techniques are similarly lacking due to the limited scale of circuits in benchmark suites and mismatches in characteristics of these circuits and those produced by random circuit generators. This paper resolves the latter of these problems by describing a random circuit generator which allows control of circuit density, width and depth parameters. This is used to derive 8000 experimental large-scale circuits and test a novel approach to compiler parallelisation. This separates a circuit into sub-circuits which are compiled in parallel and recombined to produce a compiled circuit. When the parallel approach was tested using Qiskit, a peak speedup of 15.56 was achieved with corresponding overheads of less than 1%.
Abstract Compiling quantum circuits is a major bottleneck in quantum computing, and given the scale required in a few years, is likely to become infeasibly long. Techniques to reduce compilation time for quantum circuits are sorely needed. Furthermore, resources to test acceleration techniques are similarly lacking due to the limited scale of circuits in benchmark suites and mismatches in characteristics of these circuits and those produced by random circuit generators. This paper resolves the latter of these problems by describing a random circuit generator which allows control of circuit density, width and depth parameters. This is used to derive 8000 experimental large-scale circuits and test a novel approach to compiler parallelisation. This separates a circuit into sub-circuits, which are compiled in parallel and recombined to produce a compiled circuit. When the parallel approach was tested using Qiskit, a peak speedup of 15.56 was achieved with corresponding overheads of less than 1%.
Quantum computers are superior to existing classical supercomputers in terms of run time for specific tasks, and various studies on quantum computers are in progress. Despite this, there is a significant gap in technology between available technologies and actual quantum computers on the noisy intermediate-scale quantum-scale. Currently, various quantum algorithms have been implemented and verified using quantum simulations. Therefore, the runtime performance of a quantum circuit can be verified in the same environment as a real quantum machine. A quantum compiler compiles quantum circuits. When a quantum circuit is compiled, logical qubits in a quantum circuit should be mapped to physical qubits, called qubit mapping. As qubit mapping is an NP-Complete problem, the compilation time increases exponentially according to the number of qubits. Therefore, various studies on effective qubit mapping techniques have been developed to accelerate the execution time. This paper proposes a new parallelized Qubit mapping algorithm. The proposed method consists of three-step processes: one circuit is divided into several circuits; the SABRE enhanced algorithm is executed on each circuit in parallel and then merged. The performance was evaluated using 10 benchmarks. The experimental results revealed an acceleration of up to 6.42x and an average speed up of 4.8x, with an average overhead of 1.03x in terms of the number of gates obtained. The proposed method outperformed the well-known modern qubit-mapping algorithm in terms of the execution time with exponential speedup improvement.
Quantum circuit synthesis and compilation are critical components in the quantum computing stack, both for contemporary quantum systems, where efficient use of limited resources is essential, as well as for large-scale fault-tolerant platforms, where computation time can be minimized. The specific characteristics of the quantum hardware determine which circuit designs and optimizations are feasible. We present a phase-gadget based method for compilation of quantum circuits using programmable multiqubit entangling gates, that are native, among others, to trapped-ions quantum computers. We use phase-gadgets in order to generically reduce circuit depths and efficiently implement them with few, high-fidelity, multiqubit gates. We test our methods on a large set of benchmark circuits and demonstrate generic circuit depth reduction and implementation error reduction.
The Noisy Intermediate-Scale Quantum (NISQ) technology is currently investigated by major players in the field to build the first practically useful quantum computer. IBM QX architectures are the first ones which are already publicly available today. However, in order to use them, the respective quantum circuits have to be compiled for the respectively used target architecture. While first approaches have been proposed for this purpose, they are infeasible for a certain set of SU(4) quantum circuits which have recently been introduced to benchmark corresponding compilers. In this work, we analyze the bottlenecks of existing compilers and provide a dedicated method for compiling this kind of circuits to IBM QX architectures. Our experimental evaluation (using tools provided by IBM) shows that the proposed approach significantly outperforms IBM's own solution regarding fidelity of the compiled circuit as well as runtime. Moreover, the solution proposed in this work has been declared winner of the IBM QISKit Developer Challenge. An implementation of the proposed methodology is publicly available at http://iic.jku.at/eda/research/ibm_qx_mapping.
Quantum compilation is a multi-pass process that translates a high-level circuit into an equivalent one executable on quantum hardware. A critical stage in this process is mapping, where additional gates are inserted to satisfy hardware constraints. Current mapping techniques often suffer from significant performance degradation—in terms of added gate count, increased circuit depth, and longer compilation times that scale with circuit size. In this work, we propose a novel methodology that enhances quantum compilation by leveraging concepts from Electronic Design Automation. Our approach partitions a quantum circuit into sub-circuits that can be compiled independently, and reformulates the mapping problem as a temporal floorplanning instance—a well-established technique in classical circuit design. We validate our method on widely used quantum circuit benchmark suites, achieving an average depth reduction of 22.05 % compared to traditional monolithic compilation chains using IBM Qiskit. Moreover, our approach reduces overall compilation time to that required for compiling the largest partition, while our partitioning-floorplanning algorithm runs, on average, two orders of magnitude faster than compiling the full circuit.
Quantum computing promises computational speedups over classical approaches for certain problem classes; however, in near term quantum and classical hybrid workflows, the overall performance is often constrained by classical processing overhead. The time cost associated with circuit compilation, which includes gate decomposition, topology aware qubit mapping, and depth optimization, together with protocol level communication such as circuit transfer and measurement result exchange, frequently exceeds the actual quantum circuit execution time and has become a critical bottleneck to practical deployment. In this paper, we propose QPanda 3.0, a high performance quantum programming framework optimized to accelerate the classical compilation path that underpins NISQ era hybrid integration. Leveraging an optimized compilation pipeline, a custom binary instruction stream (OriginBIS), and hardware aware execution strategies, QPanda 3.0 achieves up to 86.9 × faster encoding and 35.6 × faster decoding than OpenQASM 2.0, as well as an average 10.7 × compilation speedup over Qiskit across the four evaluated connectivity topologies, with a peak speedup of 597 × for a 118-qubit W-state circuit on a square topology. These capabilities enable the development of scalable quantum algorithms across various domains, including finance, materials science, and combinatorial optimization, supporting both industrial deployment and cloud based execution in hybrid computing environments.