Quantum compilation is a multi-pass process that translates a high-level circuit into an equivalent one executable on quantum hardware. A critical stage in this process is mapping, where additional gates are inserted to satisfy hardware constraints. Current mapping techniques often suffer from significant performance degradation—in terms of added gate count, increased circuit depth, and longer compilation times that scale with circuit size. In this work, we propose a novel methodology that enhances quantum compilation by leveraging concepts from Electronic Design Automation. Our approach partitions a quantum circuit into sub-circuits that can be compiled independently, and reformulates the mapping problem as a temporal floorplanning instance—a well-established technique in classical circuit design. We validate our method on widely used quantum circuit benchmark suites, achieving an average depth reduction of 22.05 % compared to traditional monolithic compilation chains using IBM Qiskit. Moreover, our approach reduces overall compilation time to that required for compiling the largest partition, while our partitioning-floorplanning algorithm runs, on average, two orders of magnitude faster than compiling the full circuit.
Quantum compilation is a multi-pass process that translates a high-level circuit into an equivalent one executable on quantum hardware. A critical stage in this process is mapping, where additional gates are inserted to satisfy hardware constraints. Current mapping techniques often suffer from significant performance degradation—in terms of added gate count, increased circuit depth, and longer compilation times that scale with circuit size. In this work, we propose a novel methodology that enhances quantum compilation by leveraging concepts from Electronic Design Automation. Our approach partitions a quantum circuit into sub-circuits that can be compiled independently, and reformulates the mapping problem as a temporal floorplanning instance—a well-established technique in classical circuit design. We validate our method on widely used quantum circuit benchmark suites, achieving an average depth reduction of 22.05 % compared to traditional monolithic compilation chains using IBM Qiskit. Moreover, our approach reduces overall compilation time to that required for compiling the largest partition, while our partitioning-floorplanning algorithm runs, on average, two orders of magnitude faster than compiling the full circuit.
Quantum circuit compilation is a multi-stage process that translates a high-level quantum circuit representation into a sequence of quantum gates that can be directly executed by a quantum machine. One of the core steps in quantum compilation is mapping, a procedure that transforms a quantum circuit into a semantically equivalent circuit while inserting additional gates to comply with the architectural constraints of the underlying quantum hardware. Current mapping techniques exhibit significant performance degradation—in terms of circuit depth and gate count—when applied to large-scale circuits containing hundreds of thousands of gates or more. In this work, we propose a novel methodology to enhance quantum compiler capabilities by adapting general principles from classical Electronic Design Automation. We model the quantum hardware as being composed of standard cells, onto which portions of the circuit are mapped using a floorplanning-based technique. This contrasts with current state-of-the-art solutions, which perform mapping at the gate level without considering any form of hierarchical abstraction. We use the ChaCha20 stream cipher as a running example to validate and explain our strategy. We evaluate our methodology using two well-known, industrial-grade quantum compilers: IBM Qiskit and Quantinuum TKET. Compared to these compilers, our approach achieves an average circuit depth reduction of 59.78% and 68.85%, respectively, and a gate count reduction of 4.07 % and 6.20 %, respectively. These results are obtained across a large set of randomly generated quantum circuit descriptions in the range of millions of gates, with varying input and output connectivity for each block in the circuit.
The current phase of quantum computing is in the Noisy Intermediate-Scale Quantum (NISQ) era. On NISQ devices, two-qubit gates such as CNOTs are much noisier than single-qubit gates, so it is essential to minimize their count. Quantum circuit synthesis is a process of decomposing an arbitrary unitary into a sequence of quantum gates, and can be used as an optimization tool to produce shorter circuits to improve overall circuit fidelity. However, the time-to-solution of synthesis grows exponentially with the number of qubits. As a result, synthesis is intractable for circuits on a large qubit scale. In this paper, we propose a hierarchical, block-by-block optimization framework, QGo, for quantum circuit optimization. Our approach allows an exponential cost optimization to scale to large circuits. QGo uses a combination of partitioning and synthesis: 1) partition the circuit into a sequence of independent circuit blocks; 2) re-generate and optimize each block using quantum synthesis; and 3) re-compose the final circuit by stitching all the blocks together. We perform our analysis and show the fidelity improvements in three different regimes: small-size circuits on real devices, medium-size circuits on noise simulations, and large-size circuits on analytical models. Using a set of NISQ benchmarks, we show that QGo can reduce the number of CNOT gates by 29.9% on average and up to 50% when compared with industrial compilers such as t|ket>. When executed on the IBM Athens system, shorter depth leads to higher circuit fidelity. We also demonstrate the scalability of our QGo technique to optimize circuits of 60+ qubits. Our technique is the first demonstration of successfully employing and scaling synthesis in the compilation toolchain for large circuits. Overall, our approach is robust for direct incorporation in production compiler toolchains.
The current phase of quantum computing is in the Noisy Intermediate-Scale Quantum (NISQ) era. On NISQ devices, two-qubit gates such as CNOTs are much noisier than single-qubit gates, so it is essential to minimize their count. Quantum circuit synthesis is a process of decomposing an arbitrary unitary into a sequence of quantum gates, and can be used as an optimization tool to produce shorter circuits to improve overall circuit fidelity. However, the time-to-solution of synthesis grows exponentially with the number of qubits. As a result, synthesis is intractable for circuits on a large qubit scale. In this paper, we propose a hierarchical, block-by-block opti-mization framework, QGo, for quantum circuit optimization. Our approach allows an exponential cost optimization to scale to large circuits. QGo uses a combination of partitioning and synthesis: 1) partition the circuit into a sequence of independent circuit blocks; 2) re-generate and optimize each block using quantum synthesis; and 3) re-compose the final circuit by stitching all the blocks together. We perform our analysis and show the fidelity improvements in three different regimes: small-size circuits on real devices, medium-size circuits on noisy simulations, and large-size circuits on analytical models. Our technique can be applied after existing optimizations to achieve higher circuit fidelity. Using a set of NISQ benchmarks, we show that QGo can reduce the number of CNOT gates by 29.9% on average and up to 50% when compared with industrial compiler optimizations such as t|ket). When executed on the IBM Athens system, shorter depth leads to higher circuit fidelity. We also demonstrate the scalability of our QGo technique to optimize circuits of 60+ qubits, Our technique is the first demonstration of successfully employing and scaling synthesis in the compilation tool chain for large circuits. Overall, our approach is robust for direct incorporation in production compiler toolchains to further improve the circuit fidelity.
The advancement of quantum computing into the utility scale requires compilation frameworks that can effectively manage the discrepancy between high-level algorithmic intent and the low-level physical constraints of contemporary hardware. Quantum circuit partitioning is a pivotal stage in this compilation pipeline, particularly when leveraging high-performance synthesis tools that are computationally bounded by the number of qubits. Existing partitioning approaches, such as ScanPartitioner [19] and QuickPartitioner [21], while effective, do not leverage structural patterns in circuits, limiting their ability to make globally informed local partitioning decisions. To address this gap, we propose a novel structural-aware quantum circuit partitioning method using a reinforcement learning (RL) framework that harnesses global circuit knowledge to guide local partitioning decisions, enabling more optimization opportunities at the sub-circuit level. Experimental results on benchmark circuits transpiled to satisfy IBM quantum hardware constraints show that our approach reduces the native two-qubit gate count compared to existing quantum circuit partitioners (ScanPartitioner and QuickPartitioner) with an average two-qubit gate reduction of 18.55% over baselines. This research establishes a scalable and robust methodology for partitioning quantum circuits, bridging the gap between exact and approximate synthesis in the Noisy Intermediate-Scale Quantum (NISQ) era and beyond.
The execution of quantum algorithms requires two key considerations. On the one hand, it should meet the connectivity constraint requirements of quantum circuit mapping for quantum architectures, and on the other hand, it needs to consider reducing the probability of errors in the execution of quantum circuits as much as possible. This paper proposes a novel optimization technique based on template matching that to satisfy both requirements. The template matching optimization method can significantly reduce the number of gates in a quantum circuit and further enhance its practicality. It stands as advanced optimization technology available today. Our method optimizes quantum logic circuits mapped onto quantum architecture by initially selecting their linear substructure. We then zone the circuit according to the gate dependency graph and optimize each block through template matching. Finally, we reorganize the circuit to obtain the optimized version as the final result. Our proposed method is amenable to various quantum architectures. To evaluate its efficacy, we conduct a comparative analysis with the t|ket⟩ and Qiskit compiler using a set of benchmark test circuits. Specifically, compare to the t|ket⟩ compiler method, the highest average optimization rate of our method can reach 25.75%. Compare with the Qiskit compiler method, the highest average optimization rate can reach 32.72%. Overall, our approach has significant optimization advantages.
Optimizing quantum circuits by reducing circuit depth is essential for improving the efficiency and scalability of quantum algorithms, particularly as quantum hardware continues to evolve. This can be achieved by restructuring quantum algorithms to allow more parallelism. A compiler is needed to automatically detect and apply these optimizations. In this work, we focus on the optimization of two fundamental quantum subroutines: GHZ state creation and CNOT/CZ chain decomposition. Traditional implementations of these subroutines suffer from linearly increasing circuit depth, which limits scalability. We propose a compiler-driven approach that automatically detects and optimizes these two fundamental quantum subroutines. Our approach reduces circuit depth through constant-depth GHZ state creation, constant depth CZ chain decomposition, and logarithmic depth recursive CNOT chain decomposition, which enhance parallel execution. Performance analysis of benchmarked algorithms shows significant reductions in depth. However, our solution also results in an increased gate count, which makes our optimization a trade-off. The gate count for the CNOT chains is doubled, where logarithmic depth reduction is achieved. The reduced circuit depth results in more efficient algorithms by reducing execution time.