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Modern Electronics Technique

Improved LDPC Decoding Algorithm and Its DSP Implementation

Lenan Wu

Published Jan 1, 2007• 0 citations
OpenAlex

Abstract

Low Density Parity Check(LDPC) codes,a new channel coding method,have been successfully applied to the Second Generation of Satellite Digital Video Broadcasting system.In message passing algorithms for LDPC decoding,Min-Sum algorithm has lower complexity compared to the basic Log BP algorithm.However,it causes 0.5 dB performance degradation.In this paper a normalized factor is optimized using Gaussian approximation density evolution algorithm.Numerical results show that the improved algorithm can reduce the gap between Min-Sum and Log-BP,without increasing complexity.Finally this improved algorithm is implemented on a digital signal processor.

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Low Density Parity Check(LDPC) codes,a new channel coding method,have been successfully applied to the Second Generation of Satellite Digital Video Broadcasting system.In message passing algorithms for LDPC decoding,Min-Sum algorithm has lower complexity compared to the basic Log BP algorithm.However,it causes 0.5 dB performance degradation.In this paper a normalized factor is optimized using Gaussian approximation density evolution algorithm.Numerical results show that the improved algorithm can reduce the gap between Min-Sum and Log-BP,without increasing complexity.Finally this improved algorithm is implemented on a digital signal processor.
To improve performance and reduce computation complexity of the low-density parity-check (LDPC) codes, a min-sum based differential decoding algorithm is proposed. The main principle is that the messages passing in the bipartite graph of the codes are the probability differences and the updates of the check nodes adopt min sum algorithm. Simulation results show that the proposed algorithm can achieve about 0.4dB performance gain over the UMP BP-Based decoding algorithm at bit error rate (BER) of under an additive white Gaussian noise (AWGN) channel. And it can obtain good performance very close to that of the BP decoding algorithm with much lower complexity.
Low-Density Parity check (LDPC) codes offer high-performance error correction near the Shannon limit which employs large code lengths and some iterations in the decoding process. The conventional decoding algorithm of LDPC is the Log Likelihood Ratio based Belief Propagation (LLR BP) which is also known as the `Sum-Product algorithm' which gives the best decoding performance and requires the most computational complexity and implementations with increased hardware complexity. Another simpler variant of this algorithm is used which is known as `min-sum algorithm' which reduces computational complexity as well as hardware complexity but with reduced accuracy. This paper analyzes the reason min-sum algorithm is more prone to errors when compared to the sum-product algorithm, and puts forward two improved algorithms which improve the performance of the min-sum algorithm with comparable algorithmic complexity.
Many classes of high-performance Low-density parity check codes are based on parity check matrices composed of permutation sub matrices. The emulation-simulation framework further allows the algorithm and implementation to be iteratively redefined to improve the error floor performance of message passing decoder. Log-Like hood-Ratio (LLR) based Belief-Propagation (BP) algorithm is presented for Low Density Parity Check codes. Numerically accurate representation of check node update computation used in LLR-BP decoding is described. The implementation of Sum-Product algorithm (SPA) within Low Density Parity Check Code (LDPC) decoder is described in this paper and the correction term is used to improve the decoding performance of min-sum algorithm (MSA). Quantization and log-tanh function approximation in sum-product decoder strongly affect which absorbing set dominates in error floor region. For LDPC decoder, bit error rate (BER) decreases with increase in the signal to noise ratio.
An improved decoding algorithm,which aims to reduce the decoding complexity of irregular low-density parity-check(LDPC) codes,is presented for implementation with digital signal processors(DSPs) with reduced computation complexity and low error floor.The algorithm uses the modified min-sum(MMS) algorithm for check node processing with the extrinsic information updated sequentially, so that it exhibits a low decoding threshold with a limited number of iterations,while reducing the node processing complexity and error floor.Tests with a fixed-point DSP show that the algorithm achieves a low error floor and low decoding threshold with low implementation complexity.
To reduce the complexity of encoder-decoder,the construction of QuasiCyclic Low-Density Parity-Check(QC-LDPC) codes was studied.A simplified method to find the systematic generator matrix from its parity check matrix was introduced which could greatly reduce the encoding complexity and realize linear encode-able codes.A modified Turbo serial message passing schedule for min-sum algorithm was applied with approximately the same performance as the sum-product algorithm,which updated messages immediately and converges fast.Based on the fixed point DSP,a high performance encoder-decoder were designed.The simulation result shows that this algorithm realizes efficient encoding and decoding with low complexity.