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Signal Processing

A study of the Design of Non-binary LDPC Decoder

Liu Fei, Haitao Li

Published Jan 1, 2012• 0 citations
OpenAlex

Abstract

This paper addresses decoder design for nonbinary quasicyclic LDPC(QC-LDPC) codes based on the extended min-sum(EMS) algorithm.It is necessary to perform quantities of recursive computation among the message vector,and only one single step operations is utilized to complete the check node update,which leads to larger decoder latency.In this paper,the novel non-binary LDPC decoder architecture is proposed to overcome this problem.Based on the rules of forward-backward algorithm,we utilize three single step operations to complete the check node update and optimize the check node update step operation.The hardware resource consumption for check node update increases slightly,but the cycle required is reduced to 1/3 of general decoder structure.The variable node update unit with fully parallel computation is presented without forward-backward,which removes recursive computation among the message vector and is of low complexity and latency.Moreover,an FPGA implementation for a(480,360) nonbinary QC-LDPC code decoder over GF(16) is designed to demonstrate the efficiency of the presented techniques.Simulation results show that the proposed design scheme can triple throughput of the decoder at the cost of less hardware resource consumption.

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This paper addresses decoder design for nonbinary quasicyclic LDPC(QC-LDPC) codes based on the extended min-sum(EMS) algorithm.It is necessary to perform quantities of recursive computation among the message vector,and only one single step operations is utilized to complete the check node update,which leads to larger decoder latency.In this paper,the novel non-binary LDPC decoder architecture is proposed to overcome this problem.Based on the rules of forward-backward algorithm,we utilize three single step operations to complete the check node update and optimize the check node update step operation.The hardware resource consumption for check node update increases slightly,but the cycle required is reduced to 1/3 of general decoder structure.The variable node update unit with fully parallel computation is presented without forward-backward,which removes recursive computation among the message vector and is of low complexity and latency.Moreover,an FPGA implementation for a(480,360) nonbinary QC-LDPC code decoder over GF(16) is designed to demonstrate the efficiency of the presented techniques.Simulation results show that the proposed design scheme can triple throughput of the decoder at the cost of less hardware resource consumption.
This paper addresses decoder design for nonbinary quasicyclic low-density parity-check (QC-LDPC) codes. First, a novel decoding algorithm is proposed to eliminate the multiplications over Galois field for check node processing. Then, a partially parallel architecture for check node processing units and an optimized architecture for variable node processing units are developed based on the new decoding algorithm. Thereafter, an efficient decoder structure dedicated to a promising class of high-performance nonbinary QC-LDPC codes is presented for the first time. Moreover, an ASIC implementation for a (620, 310) nonbinary QC-LDPC code decoder over GF(32) is designed to demonstrate the efficiency of the presented techniques.
Non-binary low-density parity check (NB-LDPC) codes are an extension of binary LDPC codes with significantly better performance.Although various kinds of low-complexity iterative decoding algorithms have been proposed, there is a big challenge for VLSI implementation of NBLDPC decoders due to its high complexity and long latency.In this brief, highly efficient check node processing scheme, which the processing delay greatly reduced, including Min-Max decoding algorithm and check node unit are proposed.Compare with previous works, less than 52% could be reduced for the latency of check node unit.In addition, the efficiency of the presented techniques is design to demonstrate for the (620, 310) NB-QC-LDPC decoder.
Nonbinary low-density parity-check (LDPC) codes are of great interest due to their better performance cover binary ones when the code length is moderate. However, the cost of decoder implementation for these LDPC codes is still very high. In this paper, a low-complexity VLSI architecture for nonbinary LDPC decoders is presented. By exploiting the intrinsic shifting and symmetry properties of nonbinary quasi-cyclic LDPC (QC-LDPC) codes, significant reduction of memory size and routing complexity can be achieved. These unique features lead to two network-efficient decoder architectures for Class-I and Class-II nonbinary QC-LDPC codes, respectively. Comparison results with the state-of-the-art designs show that for the code example of the 64-ary (1260, 630) rate-0.5 Class-I code, the proposed scheme can save up to 70.6% hardware required by switch network, which demonstrates the efficiency of the proposed technique. The proposed design for the 32-ary (992, 496) rate-0.5 Class-II code can achieve a 93.8% switch network complexity reduction compared with conventional approaches. Furthermore, with the help of a generator for possible solution sequences, both forward and backward steps can be eliminated to offer processing convenience of check node unit (CNU) blocks. Results show the proposed 32-ary (992, 496) rate-0.5 Class-II decoder can achieve 4.47 Mb/s decoding throughput at a clock speed of 150 MHz.
Short non-binary (NB) low-density parity-check (LDPC) codes provide excellent error rate performance compared to their binary counterparts. This paper presents an efficient layered decoder architecture for short high-order non-binary LDPC codes. A hardware-friendly message-adaptation extended Min-Sum (MA-EMS) algorithm is proposed, where a variety of truncation sizes and message compressions are used, such that the number of decoding cycles and the storage requirements can be reduced. A configurable design that supports a variety of truncation sizes is also proposed such that the hardware efficiency can be significantly increased. An early termination (ET) scheme is used so as to decrease the required number of decoding cycles. These techniques can greatly reduce the complexity of the decoder with almost no loss in performance. To demonstrate these techniques, a (64, 32) 256-ary LDPC decoder is implemented in a 90 nm process, which can provide a throughput of 322.9 Mbps and occupies an area of 6.74 mm2. The proposed MA-EMS decoder is able to achieve a similar error-rate performance and a much better area efficiency compared to the original EMS decoder.
Non-binary low-density parity-check (NB-LDPC) codes can achieve higher coding gain than binary LDPC codes when the code length is moderate at the cost of higher complexity. One major step of NB-LDPC decoding is check node processing. Previously, iterative forward-backward approaches are employed to implement this step. However, the storage of the intermediate results of the forward and backward computations requires large memory. In this paper, a novel check node processing scheme and corresponding VLSI architectures are proposed for the extended Min-sum NB-LDPC decoding. The proposed scheme only stores a limited number of sorted variable-to-check messages. Then the check-to-variable messages for different variable node are generated independently. For a (837, 726) NB-LDPC code over GF(25), the proposed architecture only requires 64% of the area of the previous design with the same throughput and error-correcting performance.