Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Architecture of a Non-binary LDPC Decoder for the Next Generation Coding Systems

David Declercq, Adrian Voicila, François S. Verdier, M.P.C. Fossorier, Pascal Urard

Published Jan 1, 2008• 0 citations
OpenAlex

Related papers

Architecture of a low-complexity non-binary LDPC decoder for high order fields

Adrian Voicila, François S. Verdier, David Declercq +2 more

In this paper, we propose a hardware implementation of the EMS decoding algorithm for non-binary LDPC codes, presented in [10]. To the knowledge of the authors this is the first implementation of a GF(q) LDPC decoder for high order fields (q ges 64). The originality of the proposed architecture is that it takes into account the memory problem of the non-binary LDPC decoders, together with a significant complexity reduction per decoding iteration which becomes independent from the field order. We present the estimation of the non-binary decoder implementation and key metrics including throughput and hardware complexity. The error decoding performance of the low complexity algorithm with proper compensation has been obtained through computer simulations. The frame error rate results are quite good with respect to the important complexity reduction. The results show also that an implementation of a non-binary LDPC decoder is now feasible and the extra complexity of the decoder is balanced by the superior performance of this class of codes. With their foreseen simple architectures and good-error correcting performances, non-binary LDPC codes provide a promising vehicle for real-life efficient coding system implementations.

International Symposium on Communications and Information Technologies•Oct 1, 2007•61 citations

Architecture of a low-complexity non-binary LDPC decoder

Adrian Voicila, David Declercq, François S. Verdier +2 more

2008 Second International Conference on Electrical Engineering•Jan 1, 2008•1 citation

Complexity evaluation of non-binary Galois field LDPC code decoders

Timo Lehnigk-Emden, Norbert Wehn

Forward error correction is an essential part of digital communication systems. Non-binary low-density parity-check (NB-LDPC) codes have an excellent communications performance for short block lengths. The higher the field size is, the better the communications performance is. Non-binary LDPC codes can outperform all other state-of-the-art code classes. However, the algorithmic decoding complexity grows with the field size. For an intended, future use of these codes in real systems, an efficient hardware implementation is mandatory. Hardware architectures for binary LDPC codes are well investigated, but efficient implementation of non-binary LDPC decoders is still an open field. To the best of our knowledge, this paper studies for the first time the hardware implementation costs for non-binary LDPC decoders with Galois field sizes of 4, 16 and 256 on FPGA and a 65nm ASIC technology.

International Symposium on Turbo Codes and Iterative Information Processing•Sep 1, 2010•25 citations

Non-binary LDPC decoder architectures

CRC Press eBooks•Jun 29, 2015•0 citations

Design and decoding algorithms of non-binary LDPC codes

Kenta Kasai, Kohichi Sakaniwa

IEICE Technical Report; IEICE Tech. Rep.•Dec 3, 2009•0 citations

A Systolic LLR Generation Architecture for Non-Binary LDPC Decoders

Ali Chamas Al Ghouwayel, Emmanuel Boutillon

Non-Binary LDPC codes offer higher performances than their binary counterpart but suffer from higher decoding complexity. A solution to reduce the decoding complexity is to use the Extended Min-Sum algorithm. The first step of this algorithm requires the generation of the first n_m largest Log-Likelihood Ratio (LLR), sorted in increasing order, of each received symbol. In the case where GF(q) symbols are transmitted using a BPSK modulation, we propose a simple systolic architecture that generates the sorted list of symbols.

IEEE Communications Letters•Jul 6, 2011•17 citations
In this paper, we propose a hardware implementation of the EMS decoding algorithm for non-binary LDPC codes, presented in [10]. To the knowledge of the authors this is the first implementation of a GF(q) LDPC decoder for high order fields (q ges 64). The originality of the proposed architecture is that it takes into account the memory problem of the non-binary LDPC decoders, together with a significant complexity reduction per decoding iteration which becomes independent from the field order. We present the estimation of the non-binary decoder implementation and key metrics including throughput and hardware complexity. The error decoding performance of the low complexity algorithm with proper compensation has been obtained through computer simulations. The frame error rate results are quite good with respect to the important complexity reduction. The results show also that an implementation of a non-binary LDPC decoder is now feasible and the extra complexity of the decoder is balanced by the superior performance of this class of codes. With their foreseen simple architectures and good-error correcting performances, non-binary LDPC codes provide a promising vehicle for real-life efficient coding system implementations.
Forward error correction is an essential part of digital communication systems. Non-binary low-density parity-check (NB-LDPC) codes have an excellent communications performance for short block lengths. The higher the field size is, the better the communications performance is. Non-binary LDPC codes can outperform all other state-of-the-art code classes. However, the algorithmic decoding complexity grows with the field size. For an intended, future use of these codes in real systems, an efficient hardware implementation is mandatory. Hardware architectures for binary LDPC codes are well investigated, but efficient implementation of non-binary LDPC decoders is still an open field. To the best of our knowledge, this paper studies for the first time the hardware implementation costs for non-binary LDPC decoders with Galois field sizes of 4, 16 and 256 on FPGA and a 65nm ASIC technology.
Non-Binary LDPC codes offer higher performances than their binary counterpart but suffer from higher decoding complexity. A solution to reduce the decoding complexity is to use the Extended Min-Sum algorithm. The first step of this algorithm requires the generation of the first n_m largest Log-Likelihood Ratio (LLR), sorted in increasing order, of each received symbol. In the case where GF(q) symbols are transmitted using a BPSK modulation, we propose a simple systolic architecture that generates the sorted list of symbols.