Design and decoding algorithms of non-binary LDPC codes

Yang Yu, Wen Chen, Jun Li +1 more

In this paper we design novel decoders for non-binary low density parity check (LDPC) codes. For a non-binary LDPC code C over the field Fqof size q for some q > 0, we propose two novel cooperative decoders, each composed of a binary component decoder and a q-ary component decoder in a concatenated manner, to obtain excellent decoding performance. Specifically to reduce the complexity of the cooperative decoders, we design a hybrid q-ary component decoder. Then, we propose an algorithm to construct the parity check matrix to eliminate the bit-level cycles. Simulations show that the decoding performance of the proposed algorithm approaches the capacity limit within 0.2dB at BER= 10−4.

健太 笠井, Kenta Kasai

Zhongxun Wang, Juan Hui

This paper is under in-depth investigation due to suspicion of possible plagiarism on a high similarity index Low Density Parity Check Code（LDPC） is a kind of linear block codes based on sparse check matrix. As a kind of channel coding, whose error performance approach Shannon limits, it has better error correction capability, more flexible structure and lower decoding complexity. Currently most of the LDPC code researches are on the premise of the AWGN channel and BSC channel, which mainly in the range of the binary LDPC codes. According to the above problem, this paper analyzes the various decoding performance of non-binary LDPC codes in Rayleigh channel, and realizes a non-binary LDPC decoder in Rayleigh channel through the FPGA design. The paper begins with an overall discussion of issues surrounding the use of non-binary LDPC codes. And then the bit-error-rate (BER) performances of different non-binary LDPC codes decoding algorithm are compared on the independent Rayleigh fading channel. Finally, this decoder design is implemented based on 5CSEMA5F31C6 FPGA (devised by Altera Company) to illustrate the concepts discussed in the paper.

Kasai Kenta

Fei Liu, Haitao Li

Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate. In this paper, we give the different initial step for different modulation and present a hardware implementation of the extended min-sum (EMS) decoding algorithm for non-binary LDPC codes. Moreover, an FPGA simulation over GF(16) is given to demonstrate the efficiency of the presented techniques.

Kuntal Deka