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Journal of PLA University of Science and Technology

Efficient encoding-decoding algorithm of QC-LDPC and DSP implementation

Bing Liu

Published Jan 1, 2008• 0 citations
OpenAlex

Abstract

To reduce the complexity of encoder-decoder,the construction of QuasiCyclic Low-Density Parity-Check(QC-LDPC) codes was studied.A simplified method to find the systematic generator matrix from its parity check matrix was introduced which could greatly reduce the encoding complexity and realize linear encode-able codes.A modified Turbo serial message passing schedule for min-sum algorithm was applied with approximately the same performance as the sum-product algorithm,which updated messages immediately and converges fast.Based on the fixed point DSP,a high performance encoder-decoder were designed.The simulation result shows that this algorithm realizes efficient encoding and decoding with low complexity.

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IEEE International Conference on Electronics, Circuits and Systems (ICECS)•Aug 1, 2008•2 citations
To reduce the complexity of encoder-decoder,the construction of QuasiCyclic Low-Density Parity-Check(QC-LDPC) codes was studied.A simplified method to find the systematic generator matrix from its parity check matrix was introduced which could greatly reduce the encoding complexity and realize linear encode-able codes.A modified Turbo serial message passing schedule for min-sum algorithm was applied with approximately the same performance as the sum-product algorithm,which updated messages immediately and converges fast.Based on the fixed point DSP,a high performance encoder-decoder were designed.The simulation result shows that this algorithm realizes efficient encoding and decoding with low complexity.
This paper presents an efficient general-purpose QC-LDPC decoder architecture by combining hardware with software.The proposed architecture can be applied to regular and irregular QC-LDPC codes of various rates,lengths and parity-check matrix structures,and supports min-sum approximation decoding algorithms and realizes different message passing scheduling strategies.Some complicated message update is implemented by a hardware accelerator,thus the decoding throughput is improved.According to the quasi-cyclic structure of the parity-check matrix,the messages are stored and processed by blocks in decoding.Parallel message processing can also be realized with a small increase in implementation complexity.
An improved decoding algorithm,which aims to reduce the decoding complexity of irregular low-density parity-check(LDPC) codes,is presented for implementation with digital signal processors(DSPs) with reduced computation complexity and low error floor.The algorithm uses the modified min-sum(MMS) algorithm for check node processing with the extrinsic information updated sequentially, so that it exhibits a low decoding threshold with a limited number of iterations,while reducing the node processing complexity and error floor.Tests with a fixed-point DSP show that the algorithm achieves a low error floor and low decoding threshold with low implementation complexity.
Quasi Cyclic Low Density Parity Check(QC-LDPC) code is an important branch of LDPC code research.It is a kind of constructed LDPC code with check matrix H constructed by quasi cyclic method.IEEE 802.16e proposes a parity check matrix with quasi cyclic character which makes the encoding and hardware easy to be implemented.This article will mainly introduce the encoding process and analyze the decoding performance of various decoding algorithms.Simulations show that Min-Sum(MS) algorithm compares to the Log-BP performance has approximately 0.5dB loss for high-speed rate coding.And the performance of Normalized Min-Sum(NMS) and Row Weight Matched Min-Sum(Rwm-MS) with relatively low complexity is nearly the same as that of Log-BP algorithm.
Low-density parity-check (LDPC) codes have attracted tremendous attention for their excellent error-correction performance and inherent fitness for high-parallelism implementation. With great complexity reduction and friendly for hardware implementation, the min-sum (MS) decoding algorithm for LDPC codes gains widespread applications in practical. In the MS decoding algorithm, finding the first two minima among input variable-to-check messages is the most complex part. To further reduce the complexity of the MS decoding algorithm, an efficient single-minimum (single-min) based layered MS decoding for quasi-cyclic LDPC (QC-LDPC) codes is proposed in this paper. It is found that statistically the difference between the first minimum and second minimum increases as the decoding becomes more convergent. Accordingly, in the proposed single-min scheme, the second minimum is approximately derived based on the first minimum and an index indicating the convergence degree. Besides, some other metrics that are easily obtained are used to refine the second minimum. Simulation results show that the proposed method can significantly improve the error-correction performance and lower the average number of iterations, compared with the state-of-the-art single-min based MS decoding algorithms.
Low Density Parity Check(LDPC) codes,a new channel coding method,have been successfully applied to the Second Generation of Satellite Digital Video Broadcasting system.In message passing algorithms for LDPC decoding,Min-Sum algorithm has lower complexity compared to the basic Log BP algorithm.However,it causes 0.5 dB performance degradation.In this paper a normalized factor is optimized using Gaussian approximation density evolution algorithm.Numerical results show that the improved algorithm can reduce the gap between Min-Sum and Log-BP,without increasing complexity.Finally this improved algorithm is implemented on a digital signal processor.
In this paper, we construct the cyclic block-type low-density parity-check (CB-LDPC) codes for low complexity hardware implementation. The CB-LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm due to the simple structure of their parity-check matrices. A distribution of irregular parity-check matrix for the CB-LDPC is developed so that we can obtain an area-efficient decoder design, good error correction performance, and low complexity architecture implementation. The CB-LDPC code decoding uses the iterative min-sum algorithm (MSA) and the block parallel connection design to improve the hardware architecture complexity and area.