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JOURNAL OF ELECTRONICS INFORMATION TECHNOLOGY

A Class of High-Rate Low-Complexity QC-LDPC Codes

Long-jiang Jing, Jing-li Lin, Zhu Wei-le

Published Mar 17, 2011• 0 citations
Publisher

Abstract

该文设计了一种特殊的高码率准循环低密度校验(QC-LDPC)码,其校验矩阵以单位矩阵的循环移位阵为基本单元,与随机构造的LDPC码相比可节省大量存储单元。利用该码校验矩阵的近似下三角特性,一种高效的递推编码方法被提出,它使得该码编码复杂度与码长成线性关系。另外,该文提出一种分析QC-LDPC码二分图中短长度环分布情况的方法,并且给出了相应的不含长为4环QC-LDPC码的构造方法。计算机仿真结果表明,新码不但编码简单,而且具有高纠错能力、低误码平层。

DOI
10.3724/sp.j.1146.2006.01738

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该文设计了一种特殊的高码率准循环低密度校验(QC-LDPC)码,其校验矩阵以单位矩阵的循环移位阵为基本单元,与随机构造的LDPC码相比可节省大量存储单元。利用该码校验矩阵的近似下三角特性,一种高效的递推编码方法被提出,它使得该码编码复杂度与码长成线性关系。另外,该文提出一种分析QC-LDPC码二分图中短长度环分布情况的方法,并且给出了相应的不含长为4环QC-LDPC码的构造方法。计算机仿真结果表明,新码不但编码简单,而且具有高纠错能力、低误码平层。
设计的一条改进欧几里德几何学的几何学途径伪周期(质量管理) 有高率、低的错误地板的低密度的同等值检查(LDPC ) 代码被论述。构造 QC-LDPC 代码与高率比原来的代码有更低的错误地板。最小的重量 codeword 的分发被分析，并且最小的重量 codeword 的一个足够的存在条件被发现。很多 QC-LDPC 与更低的错误地板编码的模拟表演能被减少最小的重量 codewords 的数字设计令人满意这个足够的条件。
Presented in this paper is a reduced-complexity iterative decoding scheme for quasi-cyclic (QC) LDPC codes. This decoding scheme is devised based on the section-wise cyclic structure of the parity-check matrix of a QC-LDPC code. Using this decoding scheme, the hardware implementation complexity of a QC-LDPC decoder can be significantly reduced without performance degradation. A high-rate QC-LDPC code that can achieve a very low error-rate without a visible error-floor is used to demonstrate the effectiveness of the proposed decoding scheme. Also presented in this paper are two other high-rate QC-LDPC codes and a method for constructing rate -1/2 QC-LDPC codes whose Tanner graphs have girth 8. All the codes constructed perform well with low error-floor using the proposed decoding scheme.
Nonbinary low-density parity-check (LDPC) codes are of great interest due to their better performance cover binary ones when the code length is moderate. However, the cost of decoder implementation for these LDPC codes is still very high. In this paper, a low-complexity VLSI architecture for nonbinary LDPC decoders is presented. By exploiting the intrinsic shifting and symmetry properties of nonbinary quasi-cyclic LDPC (QC-LDPC) codes, significant reduction of memory size and routing complexity can be achieved. These unique features lead to two network-efficient decoder architectures for Class-I and Class-II nonbinary QC-LDPC codes, respectively. Comparison results with the state-of-the-art designs show that for the code example of the 64-ary (1260, 630) rate-0.5 Class-I code, the proposed scheme can save up to 70.6% hardware required by switch network, which demonstrates the efficiency of the proposed technique. The proposed design for the 32-ary (992, 496) rate-0.5 Class-II code can achieve a 93.8% switch network complexity reduction compared with conventional approaches. Furthermore, with the help of a generator for possible solution sequences, both forward and backward steps can be eliminated to offer processing convenience of check node unit (CNU) blocks. Results show the proposed 32-ary (992, 496) rate-0.5 Class-II decoder can achieve 4.47 Mb/s decoding throughput at a clock speed of 150 MHz.
A class of rate-compatible (RC) quasi-cycle low-density parity-check (QC-LDPC) codes that have linear encodable complexity and low error floor is presented. To ensure linear encoding complexity, a lower triangular (LT) form for the parity part of the mother parity-check matrix is designed. By the designed LT form, a recursive encoding strategy is proposed. This encoding strategy can achieve linear encodable complexity, which is completely proportional to the code length. To guarantee good performances for a wide range of code rates, a layered short-cycle optimization algorithm is designed to obtain good girth distribution, and a layered density evolution algorithm is used to optimize degree distributions of each code rate. Then, a class of RC QC-LDPC codes can be obtained by both extension and puncturing from the optimized QC-LDPC mother code with rate 1/2. Simulation results show that no error floor is exhibited for the proposed RC QC-LDPC codes at FER=10-5. The practical performance at BER=10-6shows a gap of about 1.477 dB to the Shannon limit.