Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

대한전자공학회 학술대회

An improved two-stage iterative decoding of LDPC codes for Lowering error floors

Shuo-chen Wang, Atabaev Doniyor, Heejong Suh

Published Jun 1, 2014• 0 citations
OpenAlex

Abstract

In iterative decoding of LDPC codes ,from the phenomenon of error floors of LDPC code is mostly caused by an undesirable structure ,know as trapping set. In this paper, we propose a improved two-stage iterative decoding to break trapping sets. This algorithm is not need to observe all the error, only need to break which trapping set effect the effectiveness. Simulation results show that the error floor performance can be significantly improved with this decoding scheme.

Related papers

A Two-Stage Iterative Decoding of LDPC Codes for Lowering Error Floors

Jingyu Kang, Li Guo Zhang, Zhi Jun Ding +1 more

In iterative decoding of LDPC codes, trapping sets often lead to high error floors. In this work, we propose a two-stage iterative decoding to break trapping sets. Simulation results show that the error floor performance can be significantly improved with this decoding scheme.

Globecom•Jan 1, 2008•16 citations

An Effective Decoding Algorithm of LDPC Codes with Lowering Error Floors

Shuo-Chen Wang, Heejong Suh

본 논문에서는, LDPC 코드의 성능을 향상시키기 위해서, LDPC 코드의 에러 플로어(error floors)를 낮추어서 복호를 수행하는 효율 좋은 알고리듬을 제안한다. 이 방법은, 바람직하지 않은 구조 때문인데, Tanner 그래프의 트래핑 세트를 줄여서 복호를 하는 방법이다. 이 알고리듬은 트래핑 세트를 줄이는 방법으로 복호의 효율성을 얻는다. 모의시험을 통해서 이 알고리듬의 개선된 성능을 확인 할 수 있었다. In this paper, in order to improve performance of LDPC codes, we propose an effective algorithm with lowering error floor of LDPC codes. This method is done by breaking trapping sets, mostly caused by an undesirable structure. This algorithm is not need to observe all the errors, only need to break the trapping sets, to effect the effectiveness. Simulation results show that its performance can be significantly improved with this decoding algorithm.

The Journal of the Korea institute of electronic communication sciences•Oct 31, 2014•1 citation

An Iterative Decoding Algorithm with Backtracking to Lower the Error-Floors of LDPC Codes

Jingyu Kang, Qin Huang, Shu Lin +1 more

Error-floors are the main reason for excluding LDPC codes from applications requiring very low bit-error rate. They are attributed to a particular structure in the codes' Tanner graphs, known as trapping sets, which traps the message-passing algorithms commonly used to decode LDPC codes, and prevents decoding from converging to the correct codeword. A technique is proposed to break trapping sets while decoding. Based on decoding results leading to a decoding failure, some bits are identified in a previous iteration and flipped and decoding is restarted. This backtracking may enable the decoder to get out of the trapped state. A semi-analytical method is also proposed to predict the error-floor after backtracking. Simulation results indicate the effectiveness of the proposed technique in lowering the error-floor. The technique, which has moderate complexity overhead, is applicable to any code without requiring a prior knowledge of the structure of its trapping sets.

IEEE Transactions on Communications•Oct 27, 2010•45 citations

A Two-Stage Decoding Algorithm to Lower the Error-Floors for LDPC Codes

Xueting Zhang, Shaoping Chen

A two-stage decoding algorithm to lower the error-floor for low-density parity-check (LDPC) codes is presented. An efficient stopping criterion is proposed to avoid unnecessary iterations in the first stage. If the stopping criterion is reached, the first stage decoding will be terminated and the second stage decoding will be started, where the unsuccessfully decoded words are re-decoded by manipulating the log-likelihood ratio (LLR) of two types of specifically selected variable nodes. Simulation results show that the proposed algorithm can effectively lower the error floor of LDPC codes while maintaining a low decoding complexity.

IEEE Communications Letters•Feb 9, 2015•12 citations

An efficient post processing scheme to lower the error floor of LDPC decoders

Wenjie Li, Jun Ting Lin, Zhongfeng Wang

Low-Density Parity-Check (LDPC) codes have extensive applications in numerous communication systems. However, iterative LDPC decoders may suffer from error floor. In this paper, a low complexity post processing scheme (PPS) is proposed to significantly improve the error correction performance of a Min-Sum based LDPC decoder in the error floor region. Instead of using trapping set elimination algorithms, the proposed PPS introduces perturbations so that a decoder can escape from undesired local maximums. After decoding failure, for these unreliable code bits, the proposed PPS generates carefully modified soft messages, which are employed in the following decoding iterations. Numerical results demonstrate that the presented PPS significantly lowers the error floor for simulated LDPC codes.

IEEE International Conference on Communication Technology (ICCT)•Oct 1, 2017•4 citations

A Modified Sum-Product Algorithm for Error Floor Reduction in LDPC Codes

Un-Hee Park, Dae-Sub Oh, Youngmin Kim +1 more

In this paper, a modified sum-product algorithm to correct bit errors captured within the trapping sets, which are produced in decoding of low-density parity-check (LDPC) codes, is proposed. Unlike the original sum-product algorithm, the proposed decoding method consists of two stages. Whether the main cause of decoding failure is the trapping sets or not is determined at the first stage. And the bit errors within the trapping sets are corrected at the second stage. In the modified algorithm, the set of failed check nodes and the transition patterns of hard-decision bits are exploited to search variable nodes in the trapping sets. After inverting information of the variable nodes, the sum-product algorithm is carried out to correct the bit errors. As a result of simulation, the proposed algorithm shows continuously improved error performance with increase in the signal-to-noise ratio. It is, therefore, considered that the modified sum-product algorithm significantly reduces or possibly eliminates the error floor in LDPC codes.

한국통신학회논문지•Jan 1, 2010•4 citations
In iterative decoding of LDPC codes ,from the phenomenon of error floors of LDPC code is mostly caused by an undesirable structure ,know as trapping set. In this paper, we propose a improved two-stage iterative decoding to break trapping sets. This algorithm is not need to observe all the error, only need to break which trapping set effect the effectiveness. Simulation results show that the error floor performance can be significantly improved with this decoding scheme.
본 논문에서는, LDPC 코드의 성능을 향상시키기 위해서, LDPC 코드의 에러 플로어(error floors)를 낮추어서 복호를 수행하는 효율 좋은 알고리듬을 제안한다. 이 방법은, 바람직하지 않은 구조 때문인데, Tanner 그래프의 트래핑 세트를 줄여서 복호를 하는 방법이다. 이 알고리듬은 트래핑 세트를 줄이는 방법으로 복호의 효율성을 얻는다. 모의시험을 통해서 이 알고리듬의 개선된 성능을 확인 할 수 있었다. In this paper, in order to improve performance of LDPC codes, we propose an effective algorithm with lowering error floor of LDPC codes. This method is done by breaking trapping sets, mostly caused by an undesirable structure. This algorithm is not need to observe all the errors, only need to break the trapping sets, to effect the effectiveness. Simulation results show that its performance can be significantly improved with this decoding algorithm.
Error-floors are the main reason for excluding LDPC codes from applications requiring very low bit-error rate. They are attributed to a particular structure in the codes' Tanner graphs, known as trapping sets, which traps the message-passing algorithms commonly used to decode LDPC codes, and prevents decoding from converging to the correct codeword. A technique is proposed to break trapping sets while decoding. Based on decoding results leading to a decoding failure, some bits are identified in a previous iteration and flipped and decoding is restarted. This backtracking may enable the decoder to get out of the trapped state. A semi-analytical method is also proposed to predict the error-floor after backtracking. Simulation results indicate the effectiveness of the proposed technique in lowering the error-floor. The technique, which has moderate complexity overhead, is applicable to any code without requiring a prior knowledge of the structure of its trapping sets.
A two-stage decoding algorithm to lower the error-floor for low-density parity-check (LDPC) codes is presented. An efficient stopping criterion is proposed to avoid unnecessary iterations in the first stage. If the stopping criterion is reached, the first stage decoding will be terminated and the second stage decoding will be started, where the unsuccessfully decoded words are re-decoded by manipulating the log-likelihood ratio (LLR) of two types of specifically selected variable nodes. Simulation results show that the proposed algorithm can effectively lower the error floor of LDPC codes while maintaining a low decoding complexity.
Low-Density Parity-Check (LDPC) codes have extensive applications in numerous communication systems. However, iterative LDPC decoders may suffer from error floor. In this paper, a low complexity post processing scheme (PPS) is proposed to significantly improve the error correction performance of a Min-Sum based LDPC decoder in the error floor region. Instead of using trapping set elimination algorithms, the proposed PPS introduces perturbations so that a decoder can escape from undesired local maximums. After decoding failure, for these unreliable code bits, the proposed PPS generates carefully modified soft messages, which are employed in the following decoding iterations. Numerical results demonstrate that the presented PPS significantly lowers the error floor for simulated LDPC codes.
In this paper, a modified sum-product algorithm to correct bit errors captured within the trapping sets, which are produced in decoding of low-density parity-check (LDPC) codes, is proposed. Unlike the original sum-product algorithm, the proposed decoding method consists of two stages. Whether the main cause of decoding failure is the trapping sets or not is determined at the first stage. And the bit errors within the trapping sets are corrected at the second stage. In the modified algorithm, the set of failed check nodes and the transition patterns of hard-decision bits are exploited to search variable nodes in the trapping sets. After inverting information of the variable nodes, the sum-product algorithm is carried out to correct the bit errors. As a result of simulation, the proposed algorithm shows continuously improved error performance with increase in the signal-to-noise ratio. It is, therefore, considered that the modified sum-product algorithm significantly reduces or possibly eliminates the error floor in LDPC codes.