The Journal of the Korea institute of electronic communication sciences

An Effective Decoding Algorithm of LDPC Codes with Lowering Error Floors

Shuo-Chen Wang, Heejong Suh

Published Oct 31, 2014• 1 citation

Abstract

본 논문에서는, LDPC 코드의 성능을 향상시키기 위해서, LDPC 코드의 에러 플로어(error floors)를 낮추어서 복호를 수행하는 효율 좋은 알고리듬을 제안한다. 이 방법은, 바람직하지 않은 구조 때문인데, Tanner 그래프의 트래핑 세트를 줄여서 복호를 하는 방법이다. 이 알고리듬은 트래핑 세트를 줄이는 방법으로 복호의 효율성을 얻는다. 모의시험을 통해서 이 알고리듬의 개선된 성능을 확인 할 수 있었다. In this paper, in order to improve performance of LDPC codes, we propose an effective algorithm with lowering error floor of LDPC codes. This method is done by breaking trapping sets, mostly caused by an undesirable structure. This algorithm is not need to observe all the errors, only need to break the trapping sets, to effect the effectiveness. Simulation results show that its performance can be significantly improved with this decoding algorithm.

DOI: 10.13067/jkiecs.2014.9.10.1111

Related papers

An improved two-stage iterative decoding of LDPC codes for Lowering error floors

Shuo-chen Wang, Atabaev Doniyor, Heejong Suh

In iterative decoding of LDPC codes ,from the phenomenon of error floors of LDPC code is mostly caused by an undesirable structure ,know as trapping set. In this paper, we propose a improved two-stage iterative decoding to break trapping sets. This algorithm is not need to observe all the error, only need to break which trapping set effect the effectiveness. Simulation results show that the error floor performance can be significantly improved with this decoding scheme.

대한전자공학회 학술대회Jun 1, 20140 citations

An Optimized Algorithm for Constructing LDPC Code with Good Performance

Heejong Suh

본 논문에서, 성능 좋은 LDPC(Low density parity check) 코드을 위한 태너(Tanner) 그래프를 생성하는 알고리듬을 제안한다. 이 알고리듬은 뎁스 컨스트렌트(depth constraints)를 유지하면서 태너 그래프의 새로운 가지를 생성한다. 이 알고리듬은 그래프의 스토핑 �V(stopping set)을 효과적으로 줄이고, 기존의 다른 알고리듬 보다도 낮은 계산복잡도를 갖는다. 모의시험을 통해서 이 알고리듬의 개선된 성능을 확인 할 수 있었다. In this paper, an algorithm having new edge growth with depth constraints for constructing Tanner graph of LDPC(Low density parity check) codes is proposed. This algorithm reduces effectively the number of small stoping set in the graph and has lower complexity than other algorithm. The simulation results shows the improved performance of the LDPC codes constructed by this algorithm.

The Journal of the Korea institute of electronic communication sciencesAug 30, 20130 citations

Design and Performance Analysis of Nonbinary LDPC Codes With Low Error-Floors

Seok-Ki Ahn, Seung-Chan Lim, Young-Oh Yang +1 more

본 논문은 오류 마루 영역에서 우수한 성능을 가지는 비이진 LDPC (low-density parity-check) 부호의 설계 방법을 제안하고 성능을 검증한다. 제안된 설계 방법은 비이진 LDPC 부호의 이진 최소 거리(binary minimum distance)를 최대화하도록 패리티 검사 행렬의 비이진 원소 값들을 결정한다. BPSK (binary phase-shift keying) 변조 방식 하에서 제안된 방법으로 설계된 비이진 LDPC 부호가 오류 마루(error floor) 영역에서 우수한 성능을 가지는 것을 Monte Carlo 시뮬레이션과 중요도 표본 추출(importance sampling) 기법을 사용하여 검증한다. In this paper we propose a design algorithm for nonbinary LDPC (low-density parity-check) codes with low error-floors. The proposed algorithm determines the nonbinary values of the nonzero entries in the parity-check matrix in order to maximize the binary minimum distance of the designed nonbinary LDPC codes. We verify the performance of the designed nonbinary LDPC codes in the error-floor region by Monte Carlo simulation and importance sampling over BPSK (binary phase-shift keying) modulation.

한국통신학회논문지Oct 31, 20130 citations

An Iterative Decoding Algorithm with Backtracking to Lower the Error-Floors of LDPC Codes

Jingyu Kang, Qin Huang, Shu Lin +1 more

Error-floors are the main reason for excluding LDPC codes from applications requiring very low bit-error rate. They are attributed to a particular structure in the codes' Tanner graphs, known as trapping sets, which traps the message-passing algorithms commonly used to decode LDPC codes, and prevents decoding from converging to the correct codeword. A technique is proposed to break trapping sets while decoding. Based on decoding results leading to a decoding failure, some bits are identified in a previous iteration and flipped and decoding is restarted. This backtracking may enable the decoder to get out of the trapped state. A semi-analytical method is also proposed to predict the error-floor after backtracking. Simulation results indicate the effectiveness of the proposed technique in lowering the error-floor. The technique, which has moderate complexity overhead, is applicable to any code without requiring a prior knowledge of the structure of its trapping sets.

IEEE Transactions on CommunicationsOct 27, 201045 citations

Improving the Error Floor Performance of LDCP Codes with Better Codes and Better Decoders

Dung Viet Nguyen

Error correcting codes are used in virtually all communication systems to ensure reliable transmission of information. In 1948, Shannon established an upper-bound on the maximum rate at which information can be transmitted reliably over a noisy channel. Reliably transmitting information with a rate close to this theoretical limit, known as the channel capacity, has been the goal of channel coding scientists for the last five decades. The rediscovery of low-density parity-check (LDPC) codes in the 1990s added much-renewed excitement in the coding community. LDPC codes are interesting because they can approach channel capacity under sub-optimum decoding algorithms whose complexity is linear in the code length. Unsurprisingly, LDPC codes quickly attained their popularity in practical applications such as magnetic storage, wireless and optical communications. One, if not the most, important and challenging problem in LDPC code research is the study and analysis of the error floor phenomenon. This phenomenon is described as an abrupt degradation in the frame error rate performance of LDPC codes in the high signal-to-noise ratio region. Error floor is harmful because its presence prevents the LDPC decoder from reaching very low probability of decoding failure, an important requirement for many applications. Not long after the rediscovery of LDPC codes, scientists established that error floor is caused by certain harmful structures, most commonly known as trapping sets, in the Tanner representation of a code. Since then, the study of error floor mostly consists of three major problems: 1) estimating error floor; 2) constructing LDPC codes with low error floor and 3) designing decoders that are less susceptible to error floor. Although some parts of this dissertation can be used as important elements in error floor estimation, our main contributions are a novel method for constructing LDPC codes with low error floor and a novel class of low complexity decoding algorithms that can collectively alleviate error floor. These contributions are summarized as follows. A method to construct LDPC codes with low error floors on the binary symmetric channel is presented. Codes are constructed so that their Tanner graphs are free of certain small trapping sets. These trapping sets are selected from the Trapping Set Ontology for the Gallager A/B decoder. They are selected based on their relative harmfulness for a given decoding algorithm. We evaluate the relative harmfulness of different trapping sets for the sum-product algorithm by using the topological relations among them and by analyzing the decoding failures on one trapping set in the presence or absence of other trapping sets. We apply this method to construct structured LDPC codes. To facilitate the discussion, we give a new description of structured LDPC codes whose parity-check matrices are arrays of permutation matrices. This description uses Latin squares to define a set of permutation matrices that have disjoint support and to derive a simple necessary and sufficient condition for the Tanner graph of a code to be free of four-cycles. A new class of bit flipping algorithms for LDPC codes over the binary symmetric channel is proposed. Compared to the regular (parallel or serial) bit flipping algorithms, the proposed algorithms employ one additional bit at a variable node to represent its "strength." The introduction of this additional bit allows an increase in the guaranteed error correction capability. An additional bit is also employed at a check node to capture information which is beneficial to decoding. A framework for failure analysis and selection of two-bit bit flipping algorithms is provided. The main component of this framework is the (re)definition of trapping sets, which are the most "compact" Tanner graphs that cause decoding failures of an algorithm. A recursive procedure to enumerate trapping sets is described. This procedure is the basis for selecting a collection of algorithms that work well together. It is demonstrated that decoders which employ a properly selected group of the proposed algorithms operating in parallel can offer high speed and low error floor decoding.

Jan 1, 20121 citation

A Two-Stage Iterative Decoding of LDPC Codes for Lowering Error Floors

Jingyu Kang, Li Guo Zhang, Zhi Jun Ding +1 more

In iterative decoding of LDPC codes, trapping sets often lead to high error floors. In this work, we propose a two-stage iterative decoding to break trapping sets. Simulation results show that the error floor performance can be significantly improved with this decoding scheme.

GlobecomJan 1, 200816 citations